LOGIC DESIGN STATE REDUCTION STATE ASSIGNMENT

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1 LOGIC DESIGN STATE REDUCTION STATE ASSIGNMENT
(very limited in Mano, Roth more details)

2 STATE REDUCTION (DURUM İNDİRGEMESİ)
When should it be done After the state diagram determination What are the benefits Number of memory elements could be reduced Unused states introduced or their number increased which causes simplifications on the combinational part of the sequential design EE3202 Ertuğrul Eriş

3 EQUIVALENT STATE DEFINITION
Different machine Z(A, X) =Z*(B, X) Same machine Z(A, X) =Z(B, X) A and B states are called «equivalent» if the output bit streams Z ve Z* are the same for any input in any lenght. Could this definition be used for testing whether two states are equivalent or not? EE3202 Ertuğrul Eriş

4 HOW TO FIND EQUIVALENT STATES
Teorem: Necessary and sufficient condition for A and B states being equivalent is Next states should be equivalent Outputs should be the same for all one-lenght inputs. For example for a two-input-machine assume that z represents output functions, and g represents next state functions, then zi (A,00) = zi (B,00) i=1,2 g (A,00) = g (B,00) zi (A,01) = zi (B,01) i=1,2 g (A,01) = g (B,01) zi (A,10) = zi (B,10) i=1,2 g (A,10) = g (B,10) zi (A,11) = zi (B,11) i=1,2 g (A,11) = g (B,11) EE3202 Ertuğrul Eriş

5 PROOF Teorem: Necessary and sufficient condition for A and B states being equivalent is Next states should be equivalent Outputs should be the same for all one-lenght inputs. Assume that X:represent an input stream with any lenght DEFINITION: Z(A, X )= Z(B, X) A=B NECESSARY CONDITION A=B Z(A, X )= Z(B, X) Z(A, X )= Z(B, X) Z(A, X X )= Z(B, X X) Z(g(A), X )= Z(g(B), X) g(A)= g(B) SUFFICIENT CONDITION g(A)= g(B) Z(g(A), X )= Z(g(B), X) EE3202 Ertuğrul Eriş

6 STATE REDUCTION BY IMPLICATION TABLE EXAMPLE FOR MEALY MACHINE
Teorem: Necessary and sufficient condition for A and B states being equivalent is Next states should be equivalent outputs should be the same for all one-lenght inputs. √ EE3202 Ertuğrul Eriş

7 STATE REDUCTION BY IMPLICATION TABLE EXAMPLE FOR MEALY MACHINE
What would be the effect on sythesis? EE3202 Ertuğrul Eriş

8 STATE REDUCTION BY IMPLICATION TABLE EXAMPLE FOR MEALY MACHINE
Ertuğrul Eriş

9 STATE REDUCTION BY STATE PARTITIONING
Partition (bölmeleme) all the states Put all the states which could be equivalent for all one-lenght inputs in the same class Partition:union of the classes give the set of all states, while intersection is empty set If two states are in the same calss then they could be equivalent If two states are from two different classes then they will not be equivalent. EE3202 Ertuğrul Eriş

10 STATE REDUCTION EXAMPLE BY PARTITIONING
S0=(a b c d e f g) z= S1 = ( c e f ) (a b d g ) x=0 ( e c f ) (d f a b ) x=1 ( d a b) (c g e a ) S2 = ( c e f ) (b) (a d) (g) x=0 ( e c f ) (f) (d a). (b) x=1 ( d a b) (g) (c e) (a) S3 = (c e) (f) (b) (a d) (g) x=0 (e c) (f) (f) (d a). (b) x=1 (d a) (b) (g) (c e) (a) S3 = S4 Teorem: Necessary and sufficient condition for A and B states being equivalent is Next states should be equivalent outputs should be the same for all one-lenght inputs. EE3202 Ertuğrul Eriş

11 STATE ASSIGNMENT (DURUM KODLAMASI)
When shoud it be done After state reduction What are the benefits State assignment will determine input functions of the memory elements and the output functions of the circuit in other words combinational part of the sequenttial circuit. How many different codes are there? n=number of state variables, then 2n codes What is the number of different assignments? m is the number of states (2n) (2n-1) (2n-2) (2n-3)… (2n-m+1 )= EE3202 Ertuğrul Eriş

12 EQUIVALENT ASSIGNMENTS
24 different assignments for a three-state machine 1. and 3. column assinments are the interchange if state variables does not effect design cost, therefore equivalent assignments 1. and 24. assinments are complement of each other, equivalent? y1y2 1 2 3 4 23 24 a 00 ,,, 11 b 01 10 c … EE3202 Ertuğrul Eriş

13 EQUIVALENT CODES/ASSIGNMENTS FOR VARIOUS FFs
A code yY 0→0 1→1 0→1 1→0 Complement A code y'Y‘ A code JK 0K K0 1K K1 Complement A code JK A code SR 10 01 Complement A code SR A code T 1 Complement A code T A code D Complement A code D EE3202 Ertuğrul Eriş

14 EQUIVALENT ASSIGNMENTS FOR SEQUENCE DETECTOR
Assignment(I) Assignment(II) Assignment (III) Present state x=0 x=1 00 11 A B,0 A,0 01 10 B C,0 C D,0 D C,1 EE3202 Ertuğrul Eriş

15 DIFFERENT ASSIGNMENTS FOR THREE AND FOUR STATE MACHINES
Assignments for three states Assignments for four states States I II III A 00 B 01 11 C 10 D EE3202 Ertuğrul Eriş

16 NUMBER OF STATES VS DIFFERENT ASSIGNMENTS
Number of state variables Nonequivalent assignments 2 1 3 4 5 140 6 420 7 840 8 9 . 16 EE3202 Ertuğrul Eriş

17 STATE ASSIGNMENTS METHODS
Boolean function complexity definition Complexity definition for a group of functiions: not easy!! Function which has less number of independen variables Function which has either low number of one’s (zero’s) or high number of ones (zeros) Increase number of first order cubes Number of states =number of FF; codes are 2n Diğer yöntemler Heuristic methods Bench marking EE3202 Ertuğrul Eriş

18 A SIMPLE METHOD RULE 1: Give neighbour codes for state pairs which goes to the same next states under the same inputs RULE 2: Give neighbour codes for next state pairs four the neighbour codes RULE 3: Give neighbour codes for state pairs which gives the same output for the same input EE3202 Ertuğrul Eriş

19 EXAMPLE EE3202 Ertuğrul Eriş

20 EXAMPLE Neighbour coding pairs ordering:
RULE 1: Give neighbour codes for state pairs which goes to the same next states under the same inputs x=0: ACEG→AC AE AG CE CG EG; DF x=1: ABDF→AB AD AF BD BF DF ; EG RULE 2: Give neighbour codes for next state pairs four the neighbour codes BC CD BE CFx2 BGx2 RULE 3: Give neighbour codes for state pairs which gives the same output for the same input (ABCDEGG) (ABCDEF) Neighbour coding pairs ordering: DF; EG; CF; BG; AE; AC; AB; AD EE3202 Ertuğrul Eriş

21 EXAMPLE Neighbour coding pairs ordering :
DF; EG; CF; BG; AE; AC; AB; AD EE3202 Ertuğrul Eriş

22 EXAMPLE EE3202 Ertuğrul Eriş

23 PROGRAM DESIGN ??? CIRCICULUM GOAL: NATIONAL/INTERNATIONAL ACCREDITION
DEPT, PROGRAM G R A D U T E S N STUDENT P R O G A M O U T C E S PROGRAM OUTCOMES P R O G A M O U T C E S FIELD QALIFICATIONS KNOWLEDGE SKILLS COMPETENCES EU/NATIONAL QUALIFICATIONS NEWCOMER STUDENT ORIENTIATION GOVERNANCE Std. questionnaire ORIENTIATION STUDENT PROFILE Std. questionnaire FACULTY STUDENT, ??? CIRCICULUM INTRERNAL CONSTITUENT Std. questionnaire EXTRERNAL CONSTITUENT EXTRERNAL CONSTITUENT REQUIREMENTS EU/NATIONAL FIELD QUALIFICATIONS PROGRAM OUTCOMES STATE, ENTREPRENEUR ALUMNI, PARENTS NGO QUESTIONNAIRES QUALITY IMP. TOOLS GOAL: NATIONAL/INTERNATIONAL ACCREDITION

24 BLOOM’S TAXONOMY ANDERSON AND KRATHWOHL (2001)
!!Listening !! Doesn’t exits in the original!!! July 2011 Ertuğrul Eriş

25 ULUSAL LİSANS YETERLİLİKLER ÇERÇEVESİ
TÜRKİYE YÜKSEKÖĞRETİM ULUSAL YETERLİKLER ÇERÇEVESİ (TYUYÇ) TYUYÇ DÜZEYİ BİLGİ Kuramsal Uygulamalı BECERİLER Kavramsal/Bilişsel KİŞİSEL VE MESLEKİ YETKİNLİKLER Bağımsız Çalışabilme ve Sorumluluk Alabilme Yetkinliği Öğrenme Yetkinliği İletişim ve Sosyal Yetkinlik Alana Özgü ve Mesleki Yetkinlik 6 LİSANS _____ EQF-LLL: 6. Düzey QF-EHEA: 1. Düzey Ortaöğretimde kazanılan yeterliklere dayalı olarak alanındaki güncel bilgileri içeren ders kitapları, uygulama araç –gereçleri ve diğer bilimsel kaynaklarla desteklenen ileri düzeydeki kuramsal ve uygulamalı bilgilere sahip olmak Alanında edindiği ileri düzeydeki kuramsal ve uygulamalı bilgileri kullanabilmek, - Alanındaki kavram ve düşünceleri bilimsel yöntemlerle inceleyebilmek, verileri yorumlayabilmek ve değerlendirebilmek, sorunları tanımlayabilmek, analiz edebilmek, kanıtlara ve araştırmalara dayalı çözüm önerileri geliştirebilmek. Uygulamada karşılaşılan ve öngörülemeyen karmaşık sorunları çözmek için bireysel ve ekip üyesi olarak sorumluluk alabilmek, - Sorumluluğu altında çalışanların mesleki gelişimine yönelik etkinlikleri planlayabilmek ve yönetebilmek - Edindiği bilgi ve becerileri eleştirel bir yaklaşımla değerlendirebilmek, öğrenme gereksinimlerini belirleyebilmek ve öğrenmesini yönlendirebilmek. - Alanıyla ilgili konularda ilgili kişi ve kurumları bilgilendirebilmek; düşüncelerini ve sorunlara ilişkin çözüm önerilerini yazılı ve sözlü olarak aktarabilmek, - Düşüncelerini ve sorunlara ilişkin çözüm önerilerini nicel ve nitel verilerle destekleyerek uzman olan ve olmayan kişilerle paylaşabilmek, - Bir yabancı dili kullanarak alanındaki bilgileri izleyebilmek ve meslektaşları ile iletişim kurabilmek (“European Language Portfolio Global Scale”, Level B1) - Alanının gerektirdiği düzeyde bilgisayar yazılımı ile birlikte bilişim ve iletişim teknolojilerini kullanabilmek (“European Computer Driving Licence”, Advanced Level). - Alanı ile ilgili verilerin toplanması, yorumlanması, duyurulması ve uygulanması aşamalarında toplumsal, bilimsel ve etik değerlere sahip olmak, - Sosyal hakların evrenselliğine değer veren, sosyal adalet bilincini kazanmış, kalite yönetimi ve süreçleri ile çevre koruma ve iş güvenliği konularında yeterli bilince sahip olmak. BLOOMS TAXONOMY October 2011 Ertuğrul Eriş

26 COURSE ASSESMENT MATRIX
EE3202 LOGIC DESIGN a b c d e f g h i j k 1. Will employ Boolean Algebra in logic circuits modelling. 3 2. Will analyse Logic Circuits which include Small Scale Integrated components, by using various methods. 1 3. Will design logic circuits which include small scale integrated components, by using various methods. 4. Will analyse logic circuits which include medium scale integrated components, by using various methods. 5. Will design logic circuits which include medium scale integrated components, by using various methods. 6. Will analyse logic circuits which include large scale integrated components, by using various methods. 7. Will design logic circuits which include large scale integrated components, by using various methods. 8. Will simulate combinational logic circuits by employing " proteus" as a tools. LEARNING OUTCOMES EE3202 Ertuğrul Eriş