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S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Chapter 2: Machines, Machine Languages, and Digital Logic Instruction.

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1 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Chapter 2: Machines, Machine Languages, and Digital Logic Instruction sets, SRC, RTN, and the mapping of register transfers to digital logic circuits

2 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Bölüm 2: Makineler, Makine Dilleri, ve Digital Logic Komut kümeleri, SRC, RTN, ve register transfer eşlemelerinden digital logic devrelere

3 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Chapter 2 Topics 2.1 Classification of Computers and Instructions 2.2 Kinds and Classes of Instruction Sets 2.3 Informal Description of the Simple RISC Computer, SRC Students may wish to consult Appendix C, Assembly and Assemblers for information about assemblers and assembly. 2.4 Formal Description of SRC using Register Transfer Notation (RTN) 2.5 RTN Description of Addressing Modes 2.6 Register Transfers and Logic Circuits: from Behavior to Hardware Students may wish to consult Appendix A, Digital Logic for additional information about Digital Logic circuits.

4 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Bölüm 2 Konular 2.1 Bilgisayar ve Komutların Sınıflandırılması 2.2 Komut Kümeleri Çeşitleri ve Sınıfları 2.3 Basit RISC Bilgisayarların Biçimsel Olmayan Tarifi, SRC Assembler ve assembly hakkında bilgi için Appendix C’ ye bakınız. 2.4 SRClerin Register Transfer Notation (RTN) kullanılarak Biçimsel Tarifi 2.5 RTN Adresleme Şekillerinin Tarifi 2.6 Register Transfers ve Logic Devreler: from Behavior to Hardware Digital Logic devreler hakkında bilgi almak için Appendix A’ya bakınız

5 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall What are the components of an ISA? Sometimes known as The Programmers Model of the machine Storage cells General and special purpose registers in the CPU Many general purpose cells of same size in memory Storage associated with I/O devices The Machine Instruction Set The instruction set is the entire repertoire of machine operations Makes use of storage cells, formats, and results of the fetch/execute cycle i. e. Register Transfers The Instruction Format Size and meaning of fields within the instruction The nature of the Fetch/Execute cycle Things that are done before the operation code is known

6 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Bir ISA’nın Bileşenleri Nedir? Bazı zamanlar, makinenin Programcı Modeli olarak da bilinir Depolama Hücreleri CPU da ki genel ve özel amaçlı register ları Bellek de ki aynı boyut daki pek çok genel amaçlı hücreler I/O aygıtları ile ilişkili depolama birimleri Makine Komut Kümesi Makine işlemlerinin hepsine komut kümesi denir. Depolama hücrelerinin kullanılması, formatlanması ve fetch/execute döngüsünün sonuçları i. e. Register Transfers Komut Biçimi Komutdaki alanların boyut ve anlamları Fetch/Execute döngüsü İşlem kodu bilinmeden önce yapılan şeyler

7 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 2.1 Programmer’s Models of Various Machines We saw in Chap. 1 a variation in number and type of storage cells

8 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 2.1 Programcı Modelinde ki Çeşitli Makineler Bölüm 1’de pek çok varyasyonda depolama hücreleri gördük

9 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall What Must an Instruction Specify? Which operation to perform:add r0, r1, r3 Ans: Op code: add, load, branch, etc. Where to find the operand or operandsadd r0, r1, r3 In CPU registers, memory cells, I/O locations, or part of instruction Place to store resultadd r0, r1, r3 Again CPU register or memory cell Location of next instructionadd r0, r1, r3 br endloop The default is usually memory cell pointed to by program counter—PC: the next instruction in sequence Sometimes there is no operand, or no result, or no next instruction. Can you think of examples? Data Flow

10 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Komut Ne Gibi Özellikleri İçerir? Hangi işlemin gerçekleştirileceği:add r0, r1, r3 Cevap: Op code: add, load, branch, etc. Operand’ların nerden bulunacağı:add r0, r1, r3 CPU register, bellek hücreleri, I/O konumu, veya komutun bir parçası Sonucun depolanacağı yeradd r0, r1, r3 CPU register veya bellek hücreleri Sonraki komutun yeriadd r0, r1, r3 br endloop Genelde bellek hücreleri program counter tarafından işaret edilir. PC: Sırdaki, sonraki komut Bazen, operand, sonuç veya sonraki komut yoktur. Ne gibi örnekler verilebilir? Veri Akışı

11 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 2.2 Accessing Memory—Reading from Memory For a Memory Read: CPU applies desired address to Address lines A 0 -A n-1 CPU issues Read command, R Memory returns the value at that address on Data lines D 0 -D b-1 and asserts the COMPLETE signal

12 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 2.2 Belleğe Ulaşılması-Bellekden Okuma For a Memory Read: CPU istenen adresleri, Adres yollarına A 0 -A n-1 uygular CPU Read komutunu işler, R Bellek adres deki değeri Data yollarından D 0 -D b-1 döndürür ve COMPLETE sinyali yollar.

13 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Figure 2.2 Accessing Memory—Writing to Memory For a Memory Write: CPU applies desired address to Address lines A 0 -A n-1 and and data to be written on Data lines D 0 -D b-1 CPU issues Write command, W Memory asserts the COMPLETE signal when the data has been written to memory.

14 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Figure 2.2 Belleğe Ulaşılması-Belleğe Yazma For a Memory Write: CPU istenen adres bilgisinin Adres yollarından A 0 -A n-1 ve yazılacak bilgi’yi de Data yollarından gönderir D 0 -D b-1 CPU Write komutunu işler, W Data belleğe yazıldıktan sonra, bellek COMPLETE sinyali yollar.

15 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Instructions Can Be Divided into 3 Classes Data movement instructions Move data from a memory location or register to another memory location or register without changing its form Load—source is memory and destination is register Store—source is register and destination is memory Arithmetic and logic (ALU) instructions Changes the form of one or more operands to produce a result stored in another location Add, Sub, Shift, etc. Branch instructions (control flow instructions) Any instruction that alters the normal flow of control from executing the next instruction in sequence Br Loc, Brz Loc2,—unconditional or conditional branches

16 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Komutlar 3 Sınıfa Ayrılabilirler Bilgi (Data) Aktarma Komutları Bilginin bellekten veya register dan, başka bir bellek veya register a biçiminin değiştirilmeden aktarımı Load—Kaynak bellektir ve ulaşılacak yer ise register dır. Store—Kaynak register dır ve ulaşılacak yer ise bellektir. Arithmetic ve logic (ALU) komutları Bir veya daha fazla operand ın formunun değiştirilerek bir sonuç üretilip, depolanmasını sağlayan komutlardır. Add, Sub, Shift, etc. Dallanma Komutları (control flow instructions) Normal şekilde işleyen komut dizilerinin sırasının değiştirilmesi için kullanılan komutlar. Br Loc, Brz Loc2,—unconditional or conditional branches

17 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tbl. 2.1 Examples of Data Movement Instructions Lots of variation, even with one instruction type Notice differences in direction of data flow left-to-right or right-to-left

18 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tbl. 2.1 Veri Aktarım Komutlarına Örnekler Bir komut çeşidinin pek çok varyasyonu vardır. Veri akışının yönündeki farklara dikkat edilmeli left-to-right veya right-to-left

19 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Table 2.2 Examples of ALU (Arithmetic and Logic Unit) Instructions InstructionMeaningMachine MULF A, B, Cmultiply the 32-bit floating point values atVAX11 mem loc’ns. A and B, store at C nabs r3, r1Store abs value of r1 in r3PPC601 ori $2, $1, 255Store logical OR of reg $ 1 with 255 into reg $2MIPS R3000 DEC R2Decrement the 16-bit value stored in reg R2DEC PDP11 SHL AX, 4Shift the 16-bit value in reg AX left by 4 bitsIntel 8086  Notice again the complete dissimilarity of both syntax and semantics

20 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Table 2.2 ALU (Arithmetic and Logic Unit) Komut Örnekleri InstructionMeaningMachine MULF A, B, Cbellekten 32 bitlik floating point değerlerin VAX11 çarpılması. A ve B, C’ye depola nabs r3, r1r1’in mutlak değeri r3’e depolanırPPC601 ori $2, $1, 255$1 reg’in 255 ile OR lanıp reg $2 ye depolanması MIPS R3000 DEC R216-bitlik değeri azaltıp reg R2 ‘ye depolaDEC PDP11 SHL AX, 4reg AX deki 16 bitlik değeri 4 bit sola öteleIntel 8086  Sözdizimi ve anlamsal farklara dikkat edin

21 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Table 2.3 Examples of Branch Instructions InstructionMeaningMachine BLSS A, TgtBranch to address Tgt if the least significant VAX11 bit of mem loc’n. A is set (i.e. = 1) bun r2Branch to location in R2 if result of previousPPC601 floating point computation was Not a Number (NAN) beq $2, $1, 32Branch to location (PC ) if contentsMIPS R3000 of $1 and $2 are equal SOB R4, LoopDecrement R4 and branch to Loop if R4  0DEC PDP11 JCXZ AddrJump to Addr if contents of register CX  0.Intel 8086

22 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Table 2.3 Dallanma Komut Örnekleri InstructionMeaningMachine BLSS A, Tgt Eğer A bellek adresinin least significant biti VAX11 set edildiyse(=1), Tgt adresine dallan bun r2eğer bir önceki işlemin sonucu sayı değilsePPC601 R2 konumuna dallan beq $2, $1, 32Eğer $1 ve $2 nin içerikleri eşitse, (PC ) MIPS R3000 konumuna dallan SOB R4, LoopEğer R4  0 ise R4 ü azalt ve Loop a dallanDEC PDP11 JCXZ AddrEğer register CX=0 ise Addr e zıpla.Intel 8086

23 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall CPU Registers Associated with Flow of Control—Branch Insts. Program counter usually contains the address of, or "points to" the next instruction Condition codes may control branch Branch targets may be contained in separate registers

24 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall CPU Registers Associated with Flow of Control—Branch Insts. Program counter genelde bir sonraki komutun adresini içerir. Durum Kodları(Condition codes) dallanmayı kontrol edebilir. Branch targets may be contained in separate registers

25 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall HLL Conditionals Implemented by Control Flow Change Conditions are computed by arithmetic instructions Program counter is changed to execute only instructions associated with true conditions ;the comparison ;conditional branch ;action if true ;action if false

26 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall HLL Conditionals Implemented by Control Flow Change Durumlar aritmetik komutlar tarafından hesaplanır. Program counter sadece doğru durumlarla ilişkili komutların işlenmesinde değiştirilir. ;karşılaştırma ;koşullu dallanma ;eğer doğru ise çalış ;eğer yanlış ise çalış

27 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall CPU Registers may have a “personality” Architecture classes are often based on where the operands and result are located and how they are specified by the instruction. They can be in CPU registers or main memory

28 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall CPU Register Çeşitleri Mimari sınıfları, genelde operandların ve sonuçların yerleşimine ve komut tarafından nasıl belirtildiğine bağlıdır. Bunlar CPU register ları veya ana bellek de olabilir.

29 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall 3, 2, 1, & 0 Address Instructions The classification is based on arithmetic instructions that have two operands and one result The key issue is “how many of these are specified by memory addresses, as opposed to being specified implicitly” A 3 address instruction specifies memory addresses for both operands and the result: R  Op1 op Op2 A 2 address instruction overwrites one operand in memory with the result: Op2  Op1 op Op2 A 1 address instruction has a register, called the accumulator register to hold one operand & the result (no address needed): Acc  Acc op Op1 A 0 address uses a CPU register stack to hold both operands and the result: TOS  TOS op SOS where TOS is Top Of Stack, SOS is Second On Stack) The 4-address instruction, hardly ever seen, also allows the address of the next instruction to specified explicitly.

30 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall 3, 2, 1, ve 0 Adres Komutları Sınıflandırma, 2 operand ve 1 sonuç içeren aritmetik komutlara dayanır. The key issue is “how many of these are specified by memory addresses, as opposed to being specified implicitly” 3 adresli komut 2 operand ve 1 result için bellek adresi belirtir: R  Op1 op Op2 2 adresli komut sonucu bir operand ın üzerine yazar: Op2  Op1 op Op2 1 adresli komut, 1 operand ve sonucu tutan accumulator register denilen bir register e sahiptir (no address needed): Acc  Acc op Op1 0 adres sonuç ve operand ı tutan CPU register yığınını kullanır: TOS  TOS op SOS where TOS is Top Of Stack, SOS is Second On Stack) 4 adresli komutta, ek olarak bir sonraki komutun adres bilgisine de yer verilir.

31 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 2.3 The 4 Address Instruction Explicit addresses for operands, result & next instruction Example assumes 24-bit addresses Discuss: size of instruction in bytes

32 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Adres Komutu Operand, sonuç ve sonraki komut için kapalı adresler Örneğin; 24-bit adrealer düşünün Discuss: komutun boyutu (byte cinsinden)

33 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 2.4 The 3 Address Instruction Address of next instruction kept in a processor state register the PC (Except for explicit Branches/Jumps) Rest of addresses in instruction Discuss: savings in instruction word size

34 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Adres Komutu Bir sonraki komutun adresi işlemci durum register’ında tutulur PC Program Counter (Except for explicit Branches/Jumps) Komuttaki kalan diğer adresler Tartışma: Komut boyutundaki tasarruf

35 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 2.5 The 2 Address Instruction Be aware of the difference between address, Op1Addr, and data stored at that address, Op1. Result overwrites Operand 2, Op2, with result, Res This format needs only 2 addresses in the instruction but there is less choice in placing data

36 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Adres Komutu Op1Addr adresi ve verinin depolandığı Op1 adresi arasındaki fark Sonuç Res olarak Operand 2 Op2’ ye yazılır Bu format sadece 2 adres bulundurur fakat verinin yerleştirileceği yer seçimi azdır.

37 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Address Instructions Special CPU register, the accumulator, supplies 1 operand and stores result One memory address used for other operand We now need instructions to load and store operands: LDA OpAddr STA OpAddr

38 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Adres Komutu Özel CPU register ları, accumulator, 1 operand sağlarlar ve sonucu depolarlar Diğer operand için bir bellek adresi kullanılır. Yükleme ve depolama işlemleri için komut a ihtiyaç var: LDA OpAddr STA OpAddr

39 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 2.7 The 0 Address Instruction Uses a push down stack in CPU Arithmetic uses stack for both operands. The result replaces them on the TOS Computer must have a 1 address instruction to push and pop operands to and from the stack

40 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Adres Komutu CPU daki push down yığını kullanılır. Arithmetic her iki operand içinde yığını kullanır. The result replaces them on the TOS Bilgisayar yığın dan operandları çekmek ve eklemek için 1 adres komutuna sahip olmalıdır.

41 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Example 2.1 Expression evaluation for 3-0 address instructions. # of instructions & # of addresses both vary Discuss as examples: size of code in each case Evaluate a = (b+c)*d-e for and 0-address machines.

42 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Example Adres Komutlarının İfade Edilmesi Adreslerin ve komutların sayısı farklılık arz edebilir. Tartışma:her durumda ki kod boyutu a = (b+c)*d-e işlemini ve 0-adresli makineler için işleyin

43 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 2.8 General Register Machines It is the most common choice in today’s general purpose computers Which register is specified by small “address” (3 to 6 bits for 8 to 64 registers) Load and store have one long & one short address: 1 1/2 addresses 2-Operand arithmetic instruction has 3 “half” addresses

44 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 2.8 Genel Register Makineleri Günümüz genel amaçlı makinelerinin en yaygın tercih edilenleridir. Register küçük adres ile belirtilir (3 to 6 bits for 8 to 64 registers) Load ve store bir uzun ve bir kısa adrese sahiptir: 1 1/2 addresses 2-Operand arithmetic komutu 3 yarım adrese sahiptir

45 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Real Machines are Not So Simple Most real machines have a mixture of 3, 2, 1, 0, 1 1/2 address instructions A distinction can be made on whether arithmetic instructions use data from memory If ALU instructions only use registers for operands and result, machine type is load-store Only load and store instructions reference memory Other machines have a mixture of register-memory and memory-memory instructions

46 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Gerçek Makineler oldukça Basit değildir. Pek çok gerçek makine 3, 2, 1, 0, 1 1/2 address komutlarının karışımına sahiptir. Farklılık bellekten veri kullanan aritmetik komutlardan oluşabilir. Eğer ALU komutları operand ve sonuçlar için sadece register kullanıyorsa, makine tipi load-store Sadece load ve store komutları belleğe referans gösterir Diğer makineler register-bellek ve bellek-bellek komutlarının karışımına shiptirler.

47 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Addressing Modes An addressing mode is hardware support for a useful way of determining a memory address Different addressing modes solve different HLL problems Some addresses may be known at compile time, e.g. global vars. Others may not be known until run time, e.g. pointers Addresses may have to be computed: Examples include: Record (struct) components: variable base(full address) + const.(small) Array components: const. base(full address) + index var.(small) Possible to store constant values without using another memory cell by storing them with or adjacent to the instruction itself.

48 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Adresleme Şekilleri Adresleme şekli, bellek adresinin kullanışlı bir şekilde belirlenmesi için donanım desteğidir. Farklı Adresleme şekilleri farklı HLL problemlerini çözer Bazı adresler derleme zamanında bilinir. örneğin: global değişkenler. Diğerleri çalışma zamanında bilinmeyebilir. örneğin: pointers Adresler hesaplanabilir.Örneğin: Kayıt (struct) Elemenları: variable base(full address) + const.(small) Dizi Elemanları: const. base(full address) + index var.(small) Sabit değişkenleri bir başka bellek hücresi kullanmadan, bitişik komutuyla birlikte depolanması mümkündür.

49 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall HLL Examples of Structured Addresses C language: rec -> count rec is a pointer to a record: full address variable count is a field name: fixed byte offset, say 24 C language: v[i] v is fixed base address of array: full address constant i is name of variable index: no larger than array size Variables must be contained in registers or memory cells Small constants can be contained in the instruction Result: need for “address arithmetic.” E.g. Address of Rec -> Count is address of Rec + offset of count. Rec  Count V  V[i]

50 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall HLL de Kalıplaşmış Adreslerin Örnekleri C dili: rec -> count rec bir kayıta işaretçidir: full address variable count alan adıdır: fixed byte offset, say 24 C dili: v[i] v dizi adresinin başlangıç noktasıdır: full address constant i değişken dizininin ismidir: dizi boyutundan büyük olamaz Değişkenler register veya bellek hücrelerinde tutulur Küçük sabitler komutlarda tutulabilir Sonuç: need for “address arithmetic.” E.g. Address of Rec -> Count is address of Rec + offset of count. Rec  Count V  V[i]

51 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 2.9 Common Addressing Modes a-d

52 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 2.9 Common Addressing Modes e-g

53 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 2.10a Example Computer, SRC Simple RISC Computer 32 general purpose registers of 32 bits 32 bit program counter, PC and instruction register (IR) 2 32 bytes of memory address space

54 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 2.10a Örnek Bilgisayar, SRC Basit RISC Bilgisayarı 32 bitlik 32 genel amaçlı register 32 bitlik program counter, PC ve instruction register (IR) 2 32 byte lık bellek adres alanı

55 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall SRC Characteristics (=) Load-store design: only way to access memory is through load and store instructions (–) Operation on 32-bit words only, no byte or half-word operations. (=) Only a few addressing modes are supported (=) ALU Instructions are 3-register type (–) Branch instructions can branch unconditionally or conditionally on whether the value in a specified register is = 0, <> 0, >= 0, or < 0. (–) Branch-and-link instructions are similar, but leave the value of current PC in any register, useful for subroutine return. (–) Can only branch to an address in a register, not to a direct address. (=) All instructions are 32-bits (1-word) long. (=) – Similar to commercial RISC machines (–) – Less powerful than commercial RISC machines.

56 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall SRC Karakteristikleri (=) Load-store tasarımı: belleğe ulaşım sadece load ve store komutlarıyla sağlanır. (–) işlemler 32 bitlik word lerdedir, byte veya half-word işlemleri yoktur. (=) Sadece birkaç adresleme şekli desteklenir. (=) ALU komutları 3-register tiplidir (–) Dallanma komutları koşullu veya koşulsuz olarak registerda belirlenen değerin = 0, <> 0, >= 0, or < 0 durumlarına göre dallanabilir. (–) dallanma-ve-bağlantı komutları benzerdir, but leave the value of current PC in any register, useful for subroutine return. (–) sadece, register daki adrese dallanabilir, direk adrese değil. (=) Bütün komutlar 32-bitlik(1 word) uzunluğundadır. (=) – Ticari RISC makinelerine benzerdir (–) – ticari RISC makinelerine göre daha güçsüzdür

57 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall SRC Basic Instruction Formats There are three basic instruction format types The number of register specifier fields and length of the constant field vary Other formats result from unused fields or parts

58 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Basit SRC Komut Formatları 3 basit komut format tipi vardır. Register belirtme alanları ve sabit alanlarının uzunluğu değişiklik gösterebilir. Kullanılmayan alan ve parçalardan diğer formatlar sonuçları

59 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 2.10 cont'd. SRC instructions (1)

60 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 2.10 cont'd. SRC instructions (2)

61 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tbl 2.4 Example Load & Store Instructions: Memory Addressing Address can be constant, constant+register, or constant+PC Memory contents or address itself can be loaded (note use of la to load a constant)

62 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tbl 2.4 Load & Store Komutlarına Örnekler: Bellek Adresleme Adres constant, constant+register, veya constant+PC şeklinde olabilir. Bellek içerikleri veya adresler kendi yüklenebilir. (note use of la to load a constant)

63 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Assembly Language Forms of Arithmetic and Logic Instructions Immediate subtract not needed since constant in addi may be negative FormatExampleMeaning neg ra, rcneg r1, r2;Negate (r1 = -r2) not ra, rcnot r2, r3;Not (r2 = r3´ ) add ra, rb, rcadd r2, r3, r4;2’s complement addition sub ra, rb, rc;2’s complement subtraction and ra, rb, rc;Logical and or ra, rb, rc;Logical or addi ra, rb, c2 addi r1, r3, 1 ;Immediate 2’s complement add andi ra, rb, c2;Immediate logical and ori ra, rb, c2;Immediate logical or

64 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Aritmetik ve Logic Komutlarının Assembly Dilindeki Formları (Immediate)Hemen çıkarma ya ihtiyaç yoktur, çünkü addi de ki sabit negatif olabilir FormatExampleMeaning neg ra, rcneg r1, r2;Negate (r1 = -r2) not ra, rcnot r2, r3;Not (r2 = r3´ ) add ra, rb, rcadd r2, r3, r4;2’nin tümleyeni toplama sub ra, rb, rc;2’nin tümleyeni çıkarma and ra, rb, rc;Mantıksal ve or ra, rb, rc;mantıksal veya addi ra, rb, c2 addi r1, r3, 1 ;Immediate 2’nin tümleyeni topla andi ra, rb, c2;Immediate mantıksal ve ori ra, rb, c2;Immediate mantıksal veya

65 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Branch Instruction Format There are actually only two branch op codes: br rb, rc, c3 ; branch to R[rb] if R[rc] meets ; the condition defined by c3 brl ra, rb, rc, c3 ; R[ra]  PC; branch as above lsbsconditionAssemly lang formExample 000neverbrlnvbrlnv r6 001alwaysbr, brlbr r5, brl r5 010if rc = 0brzr, brlzrbrzr r2, r4 011if rc  0brnz, brlnz 100if rc ≥ 0brpl, brlpl 101if rc < 0brmi, brlmi It is c3, the 3 lsbs of c3, that governs what the branch condition is: Note that branch target address is always in register R[rb]. It must be placed there explicitly by a previous instruction.

66 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Dallanma Komutları Formatı Sadece iki dallanma opcode u vardır: br rb, rc, c3 ; R[rb] ye dallan eger R[rc] c3 deki şartla uyuşuyorsa brl ra, rb, rc, c3 ; R[ra]  PC; yukardaki gibi dallan lsbsconditionAssemly lang formExample 000neverbrlnvbrlnv r6 001alwaysbr, brlbr r5, brl r5 010if rc = 0brzr, brlzrbrzr r2, r4 011if rc  0brnz, brlnz 100if rc ≥ 0brpl, brlpl 101if rc < 0brmi, brlmi It is c3, the 3 lsbs of c3, dallanma şartının ne olduğunu yönetir: Dallanma hedefi adresi genelde R[rb] register ındadır. It must be placed there explicitly by a previous instruction.

67 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Table 2.6 Dallanma Komutları(Branch Instruction) Examples

68 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Dallanma Komutları(Branch Instructions)—Example C: goto Label3 SRC: lar r0, Label3; put branch target address into tgt reg. br r0; and branch Label3

69 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Example of conditional branch in C:#define Cost 125 if (X<0) then X = -X; in SRC: Cost.equ125;define symbolic constant.org1000;next word will be loaded at address X:.dw1;reserve 1 word for variable X.org5000;program will be loaded at location larr31, Over;load address of “false” jump location ldr1, X;load value of X into r1 brplr31, r1;branch to Else if r1≥0 negr1, r1;negate value Over: ;continue

70 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Koşullu dallanma örnekleri in C:#define Cost 125 if (X<0) then X = -X; in SRC: Cost.equ125;sembolik sabit tanımla.org1000;sonraki word adresine yüklenir X:.dw1;X değişkeni için 1 word ayrılır.org5000; konumuna program yüklenir. larr31, Over;load address of “false” jump location ldr1, X;X in değerini r1 e yükle brplr31, r1; Else if r1≥0 se dallan negr1, r1;değeri negatifle Over: ;devam et

71 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall RTN (Register Transfer Notation) Provides a formal means of describing machine structure and function Is at the “just right” level for machine descriptions Does not replace hardware description languages. Can be used to describe what a machine does (an Abstract RTN) without describing how the machine does it. Can also be used to describe a particular hardware implementation (A Concrete RTN) At first you may find this “meta description” confusing, because it is a language that is used to describe a language. You will find that developing a familiarity with RTN will aid greatly in your understanding of new machine design concepts. We will describe RTN by using it to describe SRC.

72 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall RTN (Register Transfer Notation) Makine yapısı ve fonksiyonlarının tanımlanmasında biçimsel bir araç sağlar Makine tanımlanması için “just right” düzeyindedir. Donanım tanımlama dili ile yer değiştirilmez. Makinenin bir şeyi nasıl yaptığına değinmeden, ne yaptığının tanımlanmasında kullanılır. (an Abstract RTN) Belirli Donanım implementasyonunun tanımlanmasında da kullanılabilir (A Concrete RTN) İlk bakışta bu “meta description”’ı karışık bulabilirsiniz, çünkü bu bir dili tanımlamada kullanılan dildir. You will find that developing a familiarity with RTN will aid greatly in your understanding of new machine design concepts. We will describe RTN by using it to describe SRC.

73 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Some RTN Features Using RTN to describe a machine’s static properties Static Properties Specifying registers IR   specifies a register named “IR” having 32 bits numbered 31 to 0 “Naming” using the := naming operator: op  4..0  := IR   specifies that the 5 msbs of IR be called op, with bits Notice that this does not create a new register, it just generates another name, or “alias” for an already existing register or part of a register.

74 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Bazı RTN Özellikleri Makinenin static özelliklerinin tanımlanmasında RTN kullanılması Static Özellikler Regiter ları Belirleme IR   IR isminde 31 den 0 a numarandırılmış 32 bitlik bir register ı belirtir “İsimlendirme” := isimlendirme işlemi kullanılır: op  4..0  := IR   IR ın 5 msbs si op denilen 4..0 a bitleri belirtir. Bu yeni bir register oluşturma değildir, sadece yeni bir isim oluşturmadır veya mevcut olan register ın veya bir parçasının isimlendirilmesidir.

75 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Using RTN to Describe Dynamic Properties Dynamic Properties Conditional expressions: (op=12)  R[ra]  R[rb] + R[rc]: ; defines the add instruction “if” condition “then” RTN Assignment Operator This fragment of RTN describes the SRC add instruction. It says, “when the op field of IR = 12, then store in the register specified by the ra field, the result of adding the register specified by the rb field to the register specified by the rc field.”

76 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Dinamic Özelliklerin Tanımlanmasında RTN Kullanılması Dynamic Özellikler Koşullu İfadeler: (op=12)  R[ra]  R[rb] + R[rc]: ; toplama(add) komutunu belirtir “eger” koşul “sonra” RTN Assignment Operator Bu RTN parçası SRC de toplama(add) ifadesini tanımlar. “IR ın op alanı 12 ise, rc alanıyla belirtilmiş register ile rb alanıyla belirlenmiş register ı toplayıp, sonucu ra alanı ile Belirlenmiş register a depolanır.”

77 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Using RTN to Describe the SRC (static) Processor State Processor state PC   : program counter (memory addr. of next inst.) IR   :instruction register Run:one bit run/halt indicator Strt:start signal R[0..31]   :general purpose registers

78 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall SRC yi tanımlamada RTN kullanılması (static) İşlemci Durumu İşlemi Durumu PC   : program counter(program sayıcı) (bir sonraki komutun bellek adresi) IR   :instruction register(komut register ı) Run:bir bit run/halt belirleyici Strt:başlama sinyali R[0..31]   :genel amaçlı register lar

79 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall RTN Register Declarations General register specifications shows some features of the notation Describes a set of 32 registers of 32-bit with names R[0] to R[31] R[0..31]   : Name of registers Register # in square brackets.. specifies a range of indices msb # lsb# Bit # in angle brackets Colon separates statements with no ordering

80 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall RTN Register Açıklaması Genel register belirtimi, bazı notasyon özelliklerini gösterir. R[0] dan R[31] e adlandırılmış 32 bitlik 32 tane register kümesinin tanımlanması R[0..31]   : Register’ın ismi Köşeli parantezlerde Register sayısı.. aralık ifade edilir msb # lsb# Bit numarları açılı parantezlerde gösterilir Colon separates statements with no ordering

81 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Memory Declaration: RTN Naming Operator Defining names with formal parameters is a powerful formatting tool Used to define word memory (big endian) Main memory state Mem[ ]  7..0  :2 32 addressable bytes of memory M[x]   := Mem[x]#Mem[x+1]#Mem[x+2]#Mem[x+3]: Dummy parameter Naming operator Concatenation operator All bits in register if no bit index given

82 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Bellek Açıklaması: RTN İsimlendirme İşlemi Biçimsel parametreler ile isimlerin belirlenmesi, güçlü biçimlendirme aracıdır Word belleğinin belirlenmesinde kullanılır(big endian) Ana Bellek Durumu Mem[ ]  7..0  :2 32 addressable bytes of memory M[x]   := Mem[x]#Mem[x+1]#Mem[x+2]#Mem[x+3]: Dummy parameter İsimlendirme işlemcisi Birleştirme İşlemcisi All bits in register if no bit index given

83 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall RTN Instruction Formatting Uses Renaming of IR Bits Instruction formats op  4..0  := IR   :operation code field ra  4..0  := IR   :target register field rb  4..0  := IR   :operand, address index, or branch target register rc  4..0  := IR   :second operand, conditional test, or shift count register c1   := IR   :long displacement field c2   := IR   :short displacement or immediate field c3   := IR   :count or modifier field

84 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall RTN Komutlarının şekillendirilmesinde IR Bitlerini yeniden isimlendirilmesinin kullanılması Komut Formatları op  4..0  := IR   :İşlem kodu alanı ra  4..0  := IR   :Hedef register alanı rb  4..0  := IR   :operand, address index veya dallanma hedef register rc  4..0  := IR   :ikinci operand, koşul testi veya öteleme sayaç register c1   := IR   :uzun yer değişim alanı c2   := IR   :kısa yer değişim veya immediate alanı c3   := IR   :sayaç veya güncelleme alanı

85 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Assembly Language for Shift Form of assembly language instruction tells whether to set c3=0 shr ra, rb, rc;Shift rb right into ra by 5 lsbs of rc shr ra, rb, count;Shift rb right into ra by 5 lsbs of inst shra ra, rb, rc;AShift rb right into ra by 5 lsbs of rc shra ra, rb, count;AShift rb right into ra by 5 lsbs of inst shl ra, rb, rc;Shift rb left into ra by 5 lsbs of rc shl ra, rb, count;Shift rb left into ra by 5 lsbs of inst shc ra, rb, rc;Shift rb circ. into ra by 5 lsbs of rc shc ra, rb, count;Shift rb circ. into ra by 5 lsbs of inst

86 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Öteleme için Assembly Dili Form of assembly language instruction tells whether to set c3=0 shr ra, rb, rc;rc nin 5 lsbs i kadar rb yi ra ya sağa ötele shr ra, rb, count;count un 5 lsbs i kadar rb yi ra ya sağa ötele shra ra, rb, rc;rc nin 5 lsbs i kadar rb yi ra ya sağa ötele shra ra, rb, count;count un 5 lsbs i kadar rb yi ra ya sağa ötele shl ra, rb, rc; rc nin 5 lsbs i kadar rb yi ra ya sola ötele shl ra, rb, count; count un 5 lsbs i kadar rb yi ra ya sola ötele shc ra, rb, rc; rc nin 5 lsbs i kadar rb yi ra ya dairesel ötele shc ra, rb, count; count un 5 lsbs i kadar rb yi ra ya dairesel ötele

87 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 2.11 RTN’in SRC ile Bağlantısı (The Relationship of RTN to SRC)

88 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall A Note about Specification Languages They allow the description of what without having to specify how. They allow precise and unambiguous specifications, unlike natural language. They reduce errors: errors due to misinterpretation of imprecise specifications written in natural language errors due to confusion in design and implementation - “human error.” Now the designer must debug the specification! Specifications can be automatically checked and processed by tools. An RTN specification could be input to a simulator generator that would produce a simulator for the specified machine. An RTN specification could be input to a compiler generator that would generate a compiler for the language, whose output could be run on the simulator.

89 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Özelleştirilmiş Diller ile İlgili Özellikler İşlemlerin nasıl gerçekleştiğini belirtmeden, ne gerçekleştirdiğinin anlatılmasını sağlarlar. Kesin ve açık tanımlama sağlarlar, doğal dillerden farklı olarak Hataları azaltırlar: Doğal dillerde yazılan kesin olmayan tanımlamaların yanlış yorumlanmasından doğan hatalar İmplementasyon ve tasarım da ki karışıklıklarda doğan hatalar - “insan hatası.” Şimdi tasarımcı tanımlamaları hata ayıklamalıdır! Tanımlamalar otomatik olarak kontrol edilebilir ve araçlar tarafından işlenebilir. RTN tanımlaması, belirli makine için simülatör üreten simülatör üreticisine girdi(input) olabilir. RTN tanımlaması, çıktısı(output) simülatörde çalıştırılan dil için derleyici oluşturan derleyici oluşturucusuna girdi(input) olabilir.

90 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Addressing Modes Described in RTN (Not SRC) Mode name AssemblerRTN meaning Use Syntax Register RaR[t]  R[a]Tmp. Var. Register indirect (Ra)R[t]  M[R[a]]Pointer Immediate #X R[t]  XConstant Direct, absolute X R[t]  M[X]Global Var. Indirect (X)R[t]  M[ M[X] ]Pointer Var. Indexed, based, X(Ra)R[t]  M[X + R[a]]Arrays, structs or displacement Relative X(PC)R[t]  M[X + PC]Vals stored w pgm Autoincrement (Ra)+R[t]  M[R[a]]; R[a]  R[a] + 1Sequential Autodecrement - (Ra)R[a]  R[a] - 1; R[t]  M[R[a]]access. Target register

91 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall RTN de Tanımlanmış Adresleme Şekilleri (Not SRC) Mode name AssemblerRTN anlamı Kullanım Söz dizimi Register RaR[t]  R[a]Tmp. Var. Register indirect (Ra)R[t]  M[R[a]]Pointer(İşaretçi) Immediate #X R[t]  XConstant(Sabit) Direct, absolute X R[t]  M[X]Global Değişken Indirect (X)R[t]  M[ M[X] ]İşaretçi Değişken Indexed, based, X(Ra)R[t]  M[X + R[a]]Diziler, structs or displacement Relative X(PC)R[t]  M[X + PC]Vals stored w pgm Autoincrement (Ra)+R[t]  M[R[a]]; R[a]  R[a] + 1Ardışık Autodecrement - (Ra)R[a]  R[a] - 1; R[t]  M[R[a]]uerişim Hedef Register

92 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Register transferinin Digital Logic Devrede Gösterimi Implementing the RTN statement A  B

93 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Çoklu Bit Register Transferi Implementing A  m..1   B  m..1 

94 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Logic Kapılarıyla Veri Aktarımının Gösterilemsi Logic kapıları veri aktarımının kontrolünde kullanılır:

95 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Multiplexer as a 2 Way Gated Merge Data from multiple sources can be selected for transmission

96 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Yol Kapısının Bileştirildiği Çoklayıcılar Çoklu kaynaklardan gelen verinin aktarın için seçilebilmesi

97 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig m-bit Multiplexer and Symbol Multiplexer gate signals G i may be produced by a binary to one-out-of-n decoder

98 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig m-bit Çoklayıcı ve Sembolü Çoklayıcı kapı sinyali Gi, a binary to one-out-of-n decoder tarafından oluşturulabilir.

99 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Separating Merged Data Merged data can be separated by gating at the right time It can also be strobed into a flip-flop when valid

100 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Birleştirilmiş Verinin Ayrılması Birleştirilmiş veri doğru zamanda kapılanarak ayrıştırılabilir. It can also be strobed into a flip-flop when valid

101 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Multiplexed Register Transfers using Gates and Strobes Selected gate and strobe determine which Register is Transferred to where. A  C, and B  C can occur together, but not A  C, and B  D

102 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Kapı ve stroboskop kullanılarak Multiplexed Register Transferi Seçilen kapı ve strobe, hangi register ın nereye transfer olacağına karar verir. A  C, ve B  C birlikte olabilir, fakat A  C, ve B  D olmaz

103 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Open-Collector NAND Gate Output Circuit

104 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Wired AND Connection of Open- Collector Gates

105 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Open Collector Wired OR Bus DeMorgan’s OR by not of AND of nots Pull-up resistor removed from each gate - open collector One pull-up resistor for whole bus Forms an OR distributed over the connection

106 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Tri-state Gate Internal Structure and Symbol

107 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Registers Connected by a Tri-state Bus Can make any register transfer R[i]  R[j] Can’t have G i = G j = 1 for i≠j Violating this constraint gives low resistance path from power supply to ground—with predictable results!

108 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Tri-state Veri yolu ile Bağlanmış Register lar Herhangi register transferi gerçekleştirilebilir R[i]  R[j] Can’t have G i = G j = 1 for i≠j Bu sınırlamaları bozmak güç kaynağından toprağa düşük dirençli yol verir.—tahmin edilebilir sonuçlar ile!

109 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Registers and Arithmetic Connected by One Bus Combinational Logic—no memory Example Abstract RTN R[3]  R[1]+R[2]; Concrete RTN Y  R[2]; Z  R[1]+Y; R[3]  Z; Control Sequence R[2] out, Y in ; R[1] out, Z in ; Z out, R[3] in ; Notice that what could be described in one step in the abstract RTN took three steps on this particular hardware

110 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Tek Yolla Register lar ve Aritmetik Bağlantısı Bağlantısal Logic—bellek yok Örnek Soyut RTN R[3]  R[1]+R[2]; Somut RTN Y  R[2]; Z  R[1]+Y; R[3]  Z; Kontrol Serisi R[2] out, Y in ; R[1] out, Z in ; Z out, R[3] in ; Soyut RTN da tek aşamada tanımlananlar, donanımda üç aşamada gerçekleştiğine dikkat ediniz

111 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Figure 2.25 Timing of the Register Transfers Discuss: difference between gating signals and strobing signals Discuss factors influencing minimum clock period.

112 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Figure 2.2 Register Transferinin Zamanlanması Tartışma: kapılama sinyalleri ile strobe sinyalleri arasındaki farklar Minimum clock perioduna etki eden faktörleri tartışma


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