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LOGIC DESIGN STATE REDUCTION STATE ASSIGNMENT (very limited in Mano, Roth more details)

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... konulu sunumlar: "LOGIC DESIGN STATE REDUCTION STATE ASSIGNMENT (very limited in Mano, Roth more details)"— Sunum transkripti:

1 LOGIC DESIGN STATE REDUCTION STATE ASSIGNMENT (very limited in Mano, Roth more details)

2 STATE REDUCTION (DURUM İNDİRGEMESİ)  When should it be done After the state diagram determination  What are the benefits Number of memory elements could be reduced Unused states introduced or their number increased which causes simplifications on the combinational part of the sequential design EE32022Ertuğrul Eriş

3 EQUIVALENT STATE DEFINITION A and B states are called «equivalent» if the output bit streams Z ve Z* are the same for any input in any lenght. Could this definition be used for testing whether two states are equivalent or not? EE32023Ertuğrul Eriş Different machine Z(A, X) =Z*(B, X) Same machine Z(A, X) =Z(B, X)

4 HOW TO FIND EQUIVALENT STATES  Teorem : Necessary and sufficient condition for A and B states being equivalent is Next states should be equivalent Outputs should be the same for all one-lenght inputs.  For example for a two-input-machine assume that z represents output functions, and g represents next state functions, then  z i (A,00) = z i (B,00) i=1,2g (A,00) = g (B,00)  z i (A,01) = z i (B,01) i=1,2g (A,01) = g (B,01)  z i (A,10) = z i (B,10) i=1,2g (A,10) = g (B,10)  z i (A,11) = z i (B,11) i=1,2g (A,11) = g (B,11) EE32024Ertuğrul Eriş

5 PROOF EE3202Ertuğrul Eriş5  Teorem : Necessary and sufficient condition for A and B states being equivalent is Next states should be equivalent Outputs should be the same for all one-lenght inputs. Assume that X:represent an input stream with any lenght DEFINITION: Z(A, X )= Z(B, X) A=B  NECESSARY CONDITION A=B Z(A, X )= Z(B, X) Z(A, X )= Z(B, X) Z(A, X X )= Z(B, X X) Z(g(A), X )= Z(g(B), X) g(A)= g(B)  SUFFICIENT CONDITION Z(A, X )= Z(B, X) g(A)= g(B) Z(g(A), X )= Z(g(B), X) Z(A, X )= Z(B, X)

6 STATE REDUCTION BY IMPLICATION TABLE EXAMPLE FOR MEALY MACHINE EE32026Ertuğrul Eriş √ Teorem: Necessary and sufficient condition for A and B states being equivalent is Next states should be equivalent outputs should be the same for all one-lenght inputs.

7 STATE REDUCTION BY IMPLICATION TABLE EXAMPLE FOR MEALY MACHINE EE32027Ertuğrul Eriş What would be the effect on sythesis?

8 STATE REDUCTION BY IMPLICATION TABLE EXAMPLE FOR MEALY MACHINE EE32028Ertuğrul Eriş

9 STATE REDUCTION BY STATE PARTITIONING  Partition (bölmeleme) all the states Put all the states which could be equivalent for all one-lenght inputs in the same class Partition:union of the classes give the set of all states, while intersection is empty set  If two states are in the same calss then they could be equivalent  If two states are from two different classes then they will not be equivalent. EE32029Ertuğrul Eriş

10 STATE REDUCTION EXAMPLE BY PARTITIONING  S 0 =(a b c d e f g)  z=  S 1 = ( c e f ) (a b d g )  x=0 ( e c f ) (d f a b )  x=1 ( d a b) (c g e a )  S 2 = ( c e f ) (b) (a d) (g)  x=0 ( e c f ) (f) (d a). (b)  x=1 ( d a b) (g) (c e) (a)  S 3 = (c e) (f) (b) (a d) (g)  x=0 (e c) (f) (f) (d a). (b)  x=1 (d a) (b) (g) (c e) (a)  S 3 = S 4 EE320210Ertuğrul Eriş Teorem: Necessary and sufficient condition for A and B states being equivalent is Next states should be equivalent outputs should be the same for all one-lenght inputs.

11 STATE ASSIGNMENT (DURUM KODLAMASI)  When shoud it be done After state reduction  What are the benefits  State assignment will determine input functions of the memory elements and the output functions of the circuit in other words combinational part of the sequenttial circuit.  How many different codes are there? n=number of state variables, then 2 n codes  What is the number of different assignments? m is the number of states (2 n ) (2 n -1) (2 n -2) (2 n -3)… (2 n -m+1 )= EE320211Ertuğrul Eriş

12 EQUIVALENT ASSIGNMENTS  24 different assignments for a three-state machine  1. and 3. column assinments are the interchange if state variables does not effect design cost, therefore equivalent assignments  1. and 24. assinments are complement of each other, equivalent? y1y2y1y a00,,,11 b01 10,,,10 c … 10 EE320212Ertuğrul Eriş

13 EQUIVALENT CODES/ASSIGNMENTS FOR VARIOUS FFs A code yY 0→01→10→11→0 Complement A code y'Y‘ 1→10→01→00→1 A code JK 0KK01KK1 Complement A code JK K00KK11K A code SR 0KK01001 Complement A code SR K00K0110 A code T 0011 Complement A code T 0011 A code D 0110 Complement A code D 1001 EE320213Ertuğrul Eriş

14 EQUIVALENT ASSIGNMENTS FOR SEQUENCE DETECTOR Assignment(I)Assignment(II)Assignment (III)Present state x=0x= AB,0A, BB,0C, CD,0A, DB,0C,1 EE320214Ertuğrul Eriş

15 DIFFERENT ASSIGNMENTS FOR THREE AND FOUR STATE MACHINES Assignments for three statesAssignments for four states StatesIIIIIIIIIIII A00 B C D1110 EE320215Ertuğrul Eriş

16 NUMBER OF STATES VS DIFFERENT ASSIGNMENTS Number of states Number of state variables Nonequivalent assignments EE320216Ertuğrul Eriş

17 STATE ASSIGNMENTS METHODS  Boolean function complexity definition Complexity definition for a group of functiions: not easy!! Function which has less number of independen variables Function which has either low number of one’s (zero’s) or high number of ones (zeros) Increase number of first order cubes Number of states =number of FF; codes are 2 n Diğer yöntemler Heuristic methods Bench marking EE320217Ertuğrul Eriş

18 A SIMPLE METHOD  RULE 1: Give neighbour codes for state pairs which goes to the same next states under the same inputs  RULE 2: Give neighbour codes for next state pairs four the neighbour codes  RULE 3: Give neighbour codes for state pairs which gives the same output for the same input EE320218Ertuğrul Eriş

19 EXAMPLE EE320219Ertuğrul Eriş

20 EXAMPLE  RULE 1: Give neighbour codes for state pairs which goes to the same next states under the same inputs x=0: ACEG → AC AE AG CE CG EG; DF x=1: ABDF → AB AD AF BD BF DF ; EG  RULE 2: Give neighbour codes for next state pairs four the neighbour codes BC CD BE CFx2 BGx2  RULE 3: Give neighbour codes for state pairs which gives the same output for the same input  (ABCDEGG) (ABCDEF)  Neighbour coding pairs ordering: DF; EG; CF; BG; AE; AC; AB; AD EE320220Ertuğrul Eriş

21 EE320221Ertuğrul Eriş Neighbour coding pairs ordering : DF; EG; CF; BG; AE; AC; AB; AD EXAMPLE

22 EE320222Ertuğrul Eriş EXAMPLE

23 PROGRAM OUTCOMES PROGRAM DESIGN ??? CIRCICULUM ??? Std. questionnaire Std. questionnaire Std. questionnaire STUDENT PROFILE DEPT, PROGRAM STUDENT NEWCOMER STUDENT QUALITY IMP. TOOLS EXTRERNAL CONSTITUENT FACULTY GOVERNANCE INTRERNAL CONSTITUENT STUDENT, STATE, ENTREPRENEUR ALUMNI, PARENTS NGO GOAL: NATIONAL/INTERNATIONAL ACCREDITION EU/NATIONAL QUALIFICATIONS EU/NATIONAL GRADUATESTUDENTGRADUATESTUDENT QUESTIONNAIRES FIELD QUALIFICATIONS KNOWLED GE SKILLS COMPETENC ES EXTRERNAL CONSTITUENT REQUIREMENTS ORIENTIATION PROGRAM OUTCOMES PROGRAMOUTCOMESPROGRAMOUTCOMES PROGRAMOUTCOMESPROGRAMOUTCOMES 23

24 BLOOM’S TAXONOMY ANDERSON AND KRATHWOHL (2001) July 2011Ertuğrul Eriş24 !!Listening !! Doesn’t exits in the original!!!

25 25 TÜRKİYE YÜKSEKÖĞRETİM ULUSAL YETERLİKLER ÇERÇEVESİ (TYUYÇ) TYUYÇ DÜZEYİ BİLGİ -Kuramsal -Uygulamalı BECERİLER -Kavramsal/Bilişsel -Uygulamalı KİŞİSEL VE MESLEKİ YETKİNLİKLER Bağımsız Çalışabilme ve Sorumluluk Alabilme Yetkinliği Öğrenme Yetkinliği İletişim ve Sosyal Yetkinlik Alana Özgü ve Mesleki Yetkinlik 6 LİSANS _____ EQF-LLL: 6. Düzey _____ QF-EHEA: 1. Düzey -Ortaöğretimd e kazanılan yeterliklere dayalı olarak alanındaki güncel bilgileri içeren ders kitapları, uygulama araç – gereçleri ve diğer bilimsel kaynaklarla desteklenen ileri düzeydeki kuramsal ve uygulamalı bilgilere sahip olmak -Alanında edindiği ileri düzeydeki kuramsal ve uygulamalı bilgileri kullanabilmek, - Alanındaki kavram ve düşünceleri bilimsel yöntemlerle inceleyebilmek, verileri yorumlayabilmek ve değerlendirebilmek, sorunları tanımlayabilmek, analiz edebilmek, kanıtlara ve araştırmalara dayalı çözüm önerileri geliştirebilmek. -Uygulamada karşılaşılan ve öngörülemeyen karmaşık sorunları çözmek için bireysel ve ekip üyesi olarak sorumluluk alabilmek, - Sorumluluğu altında çalışanların mesleki gelişimine yönelik etkinlikleri planlayabilmek ve yönetebilmek - Edindiği bilgi ve becerileri eleştirel bir yaklaşımla değerlendirebil mek, öğrenme gereksinimlerin i belirleyebilmek ve öğrenmesini yönlendirebilm ek. - Alanıyla ilgili konularda ilgili kişi ve kurumları bilgilendirebilmek; düşüncelerini ve sorunlara ilişkin çözüm önerilerini yazılı ve sözlü olarak aktarabilmek, - Düşüncelerini ve sorunlara ilişkin çözüm önerilerini nicel ve nitel verilerle destekleyerek uzman olan ve olmayan kişilerle paylaşabilmek, - Bir yabancı dili kullanarak alanındaki bilgileri izleyebilmek ve meslektaşları ile iletişim kurabilmek (“European Language Portfolio Global Scale”, Level B1) - Alanının gerektirdiği düzeyde bilgisayar yazılımı ile birlikte bilişim ve iletişim teknolojilerini kullanabilmek (“European Computer Driving Licence”, Advanced Level). - Alanı ile ilgili verilerin toplanması, yorumlanması, duyurulması ve uygulanması aşamalarında toplumsal, bilimsel ve etik değerlere sahip olmak, - Sosyal hakların evrenselliğine değer veren, sosyal adalet bilincini kazanmış, kalite yönetimi ve süreçleri ile çevre koruma ve iş güvenliği konularında yeterli bilince sahip olmak. ULUSAL LİSANS YETERLİLİKLER ÇERÇEVESİ BLOOMS TAXONOMY October 2011Ertuğrul Eriş

26 COURSE ASSESMENT MATRIX EE3202 LOGIC DESIGNabcdefghijk 1. Will employ Boolean Algebra in logic circuits modelling Will analyse Logic Circuits which include Small Scale Integrated components, by using various methods Will design logic circuits which include small scale integrated components, by using various methods Will analyse logic circuits which include medium scale integrated components, by using various methods Will design logic circuits which include medium scale integrated components, by using various methods Will analyse logic circuits which include large scale integrated components, by using various methods Will design logic circuits which include large scale integrated components, by using various methods Will simulate combinational logic circuits by employing " proteus" as a tools Will employ Boolean Algebra in logic circuits modelling EE3202Ertuğrul Eriş26 LEARNING OUTCOMES


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