S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Chapter 6 Overview Number Systems and Radix Conversion Fixed point arithmetic Seminumeric Aspects of ALU Design Floating Point Arithmetic

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Digital Number Systems Digital number systems have a base or radix b Using positional notation, an m digit base b number is written x = x m-1 x m-2... x 1 x 0 0 ≤ x i ≤ b-1, 0 ≤ i < m The value of this unsigned integer is

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Dijital Sayı Sistemi Digital number systems have a base or radix b Durumsal gösterim (positional notation),kullanılması bir m rakamı base b sayısı şu şekilde yazılır x = x m-1 x m-2... x 1 x 0 0 ≤ x i ≤ b-1, 0 ≤ i < m Bu unsigned integer’ın değeri şudur.

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Radix Conversion: General Matters Converting from one number system to another involves computation We call the base in which calculation is done c and the other base b Calculation is based on the division algorithm — For integers a & b, there exist integers q & r such that a = q  b + r, with 0 ≤ r ≤ b-1 Notation: q =  a/b  r = a mod b

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Radix Dönüşümü: Genel Durumlar Bir sayı sistemini bir başka sisteme dönüştürmek hesaplama gerektirir Hesaplamanın yapıldığı tabana c, diğer tabana b diyelim Hesaplama bölme algoritması baz alınarak yapılır —a & b sayıları için, q & r olarak şu tam sayılar mevcut olsun a = q  b + r, with 0 ≤ r ≤ b-1 Gösterimi: q =  a/b  r = a mod b

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Convert Base b Integer to Calculator’s Base, c 1) Start with base b x = x m-1 x m-2... x 1 x 0 2) Set x = 0 in base c 3) Left to right, get next symbol x i 4) Lookup base c number D i for symbol x i 5) Calculate in base c: x = x  b + D i 6) If there are more digits, repeat from step 3 Example: convert 3AF 16 to base 10 x = 0 x = 16x + 3 = 3 x = 16  x  F 

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Base b tam sayısının Base, c ye çevrilmesi 1) Base b ile başlayalım x = x m-1 x m-2... x 1 x 0 2) Base c de x = 0 3) Soldan sağa sonraki x i sembolünü alalım 4) x i Sembolü için base c number D i yi arayalım 5) base c de hesaplayalım: x = x  b + D i 6) Eğer daha fazla rakam varsa basamak 3 den tekrarlayalım Örnek: 3AF 16 yı 10 tabanına çevirelim x = 0 x = 16x + 3 = 3 x = 16  x  F 

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Convert Calculator’s Base Integer to Base b 1) Let x be the base c integer 2) Initialize i = 0 and v = x & get digits right to left 3) Set D i = v mod b & v =  v/b . Lookup D i to get x i 4) i = i + 1; If v  0, repeat from step 3 Example: convert to base  12 = 298 (rem = 11)  x 0 = B 298  12 = 24 (rem = 10)  x 1 = A 24  12 = 2 (rem = 0)  x 2 = 0 2  12 = 0 (rem = 2)  x 3 = 2 Thus = 20AB 12

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Convert Calculator’s Base Integer to Base b 1) X base c nin sayısı olsun 2) Initialize i = 0 ve v = x & sağdan sola rakamları alalım 3) Set D i = v mod b & v =  v/b . x i elde etmek için D i arayalım 4) i = i + 1; If v  0, basamak 3 den tekrar edelim Örnek: yi 12 lik tabana çevirin 3587  12 = 298 (rem = 11)  x 0 = B 298  12 = 24 (rem = 10)  x 1 = A 24  12 = 2 (rem = 0)  x 2 = 0 2  12 = 0 (rem = 2)  x 3 = 2 Thus = 20AB 12

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fractions and Fixed Point Numbers The value of the base b fraction.f -1 f -2...f -m is the value of the integer f -1 f -2...f -m divided by b m The value of a mixed fixed point number x n-1 x n-2...x 1 x 0.x -1 x -2...x -m is the value of the n+m digit integer x n-1 x n-2...x 1 x 0 x -1 x -2...x -m divided by b m Moving radix point one place left divides by b For fixed radix point position in word, this is a right shift of word Moving radix point one place right multiplies by b For fixed radix point position in word, this is a left shift of word

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fractions(Kesir) and Fixed Point Numbers Taban b nin f -1 f -2...f -m kesirlerinin değeri f -1 f -2...f -m sayılarının b m ile bölümüdür. x n-1 x n-2...x 1 x 0.x -1 x -2...x -m mixed fixed point number ın değeri n+m rakamlı x n-1 x n-2...x 1 x 0 x -1 x -2...x -m sayısının b m ile bölümüdür radix noktasının bir konum sola hareketi b ile bölünmesidir For fixed radix point position in word, this is a right shift of word radix noktasında bir konum sağa hareket b ile çarpmadır For fixed radix point position in word, this is a left shift of word

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Converting Fraction to Calculator’s Base An algorithm 1) Let base b number be.f -1 f -2...f -m 2) Initialize f = 0.0 and i = -m 3) Find base c equivalent D of f i 4) f = (f + D)/b; i = i + 1 5) If i = 0, the result is f. Otherwise repeat from 3 Example: convert to base 10 f = (0 + 3)/8 =.375 f = ( )/8 = f = ( )/8 =

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Kesirlerin hesap makinesi tabanına çevrilmesi Algoritma 1) Let base b number be.f -1 f -2...f -m 2) Initialize f = 0.0 and i = -m 3) Find base c equivalent D of f i 4) f = (f + D)/b; i = i + 1 5) If i = 0, the result is f. Otherwise repeat from 3 Örnek: sayısını 10 luk tabana çevirelim f = (0 + 3)/8 =.375 f = ( )/8 = f = ( )/8 =

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Non-terminating Fractions The division in the algorithm may give a non-terminating fraction in the calculator’s base This is a general problem A fraction of m digits in one base may have any number of digits in another base The calculator will normally keep only a fixed number of digits Number should make base c accuracy about that of base b The algorithm can continue to generate digits unless terminated

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Sonlanmayan Kesirler(devreden Kesirli sayılar) Algoritma daki bölmeler, hesap makinesi tabanında sonlanmayan kesir sonucu verebilir Bu genek bir problemdir Bir tabanda M basamaklı kesir bir başka tabanda herhangi bir basamak sayısında sonuç verebilir. Hesap makinesi sadece sabit bir sayıda basamak tutar Number should make base c accuracy about that of base b Sonlanmadıkça algoritma basamak oluşturmaya devam edebilir

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Convert Fraction from Calculator’s Base to Base b 1) Start with exact fraction f in base c 2) Initialize i = 1 and v = f 3) D -i =  b  v  ; v = b  v - D -i ; Get base b f -i for D -i 4) i = i + 1; repeat from 3 unless v = 0 or enough base b digits have been generated Example: convert to base 8.31  8 = 2.48  f -1 = 2.48  8 = 3.84  f -2 = 3.84  8 = 6.72  f -1 = 6 Since 8 3 > 10 2, has more accuracy than.31 10

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Hesap makinesi tabanındaki kesirlerin b tabanına çevrilmesi 1) Taban c de f kesiri ile başlanır 2) i = 1 ve v = f olarak tanımlanır 3) D -i =  b  v  ; v = b  v - D -i ; Get base b f -i for D -i 4) i = i + 1; v = 0 olmadıkça veya yeteri kadar taban b basamağı oluşturulmadıkça 3 tekrar edilir örnek: sayısını 8 tabanına çevirelim.31  8 = 2.48  f -1 = 2.48  8 = 3.84  f -2 = 3.84  8 = 6.72  f -1 = 6 Since 8 3 > 10 2, has more accuracy than.31 10

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Conversion Between Related Bases by Digit Grouping Examples: = = 49C 16 49C 16 = = = =

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Negative Numbers, Complements, & Complement Representations Complement operations? Complement number systems? Systems represent both positive and negative numbers Relation between complement and negate in a complement number system? Relation between shifting and scaling a number by a power of the base?

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Negative Numbers, Complements, & Complement Representations Complement operations? Complement number systems? Pozitif ve negatif sayıların gösterilmesi Complement sayı sisteminde complement ve negate arasındaki ilişki? Bir sayının bir tabanın kuvveti oranında shifting ve scaling işlemleri arasındaki ilişki?

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Complement Operations— for m Digit Base b Numbers Radix complement of m digit base b number x x c = (b m - x) mod b m Diminished radix complement of x x c = b m x The complement of a number in the range 0  x  b m -1 is in the same range

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Complement İşlemleri— m basamaklı taban b şeklindeki sayılar için Radix complement of m digit base b number x x c = (b m - x) mod b m X in Diminished radix complement’i x c = b m x Bir sayının 0  x  b m -1 arasındaki complement’i aynı aralıktadır

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Complement Number Systems Complement number systems use unsigned numbers to represent both positive and negative numbers The range of an m digit base b unsigned number is 0  x  b m -1 The first half of the range is used for positive, and the second half for negative numbers Positive numbers are simply represented by the unsigned number corresponding to their absolute value

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Complement Sayı Sistemleri Complement sayı sistemleri pozitif ve negatif sayıları ifade etmek için unsigned number kullanırlar. bir m digit base b unsigned sayının aralığı 0  x  b m -1 Aralığın ilk yarısı pozitif ler için ikinci yarısı negatifler için kullanılır Pozitif sayılar, mutlak değerlerine tekabül eden unsigned sayı ile kolayca ifade edilir.

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Use of Complements to Represent Negative Numbers The complement of a number in the range from 0 to b m /2 is in the range from b m /2 to b m -1 A negative number is represented by the complement of its absolute value There are an equal number (±1) of positive and negative number representations The ±1 depends on whether b is odd or even and whether radix complement or diminished radix complement is used The usual sign-magnitude system introduces extra symbols + & - in addition to the digits In binary, it is easy to map 0  + and 1  - In base b>2, using a whole digit for the two values + & - is wasteful

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Negatif sayıların complement kullanılarak ifade edilmesi Bir sayının 0 to b m /2 aralığından complement’i b m /2 den b m -1 aralığındadır. Bir negatif sayı, kendisinin mutlak değerinin complement ile ifade edilir. There are an equal number (±1) of positive and negative number representations The ±1 depends on whether b is odd or even and whether radix complement or diminished radix complement is used The usual sign-magnitude system introduces extra symbols + & - in addition to the digits Binary sayılarda, 0  + ve 1  - ifade eder b>2 tabanlarda, bütün rakamların + ve- değerleri için kullanılması israfdır

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Table 6.1 Complement Representations of Negative Numbers Radix ComplementDiminished Radix Complement Number Representation 0000 or b m -1 0<x<b m /2x x -b m /2  x<0 |x| c = b m - |x| |x| c = b m |x| -b m /2<x<0

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Table 6.2 Base 2 Complement Representations In 1’s complement, 255 = is often called -0 In 2’s complement, -128 = is a legal value, but trying to negate it gives overflow 8 Bit 2’s Complement8 Bit 1’s Complement Number Representation 0000 or 255 0<x<128x x -128  x< |x| |x| -127  x<0

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Table 6.2 Base 2 Complement Representations 1’s complement de, 255 = olarak bilinir 2’s complement de, -128 = legal bir değerdir, fakat negate etmeye çalışmak overflow oluşturur 8 Bit 2’s Complement8 Bit 1’s Complement Number Representation 0000 or 255 0<x<128x x -128  x< |x| |x| -127  x<0

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Table Driven Calculation of Complements in Base 5 4’s complement of is ’s complement of is = ’s complement of is = ’s complement of is ( ) mod 5 5 = Base 5 Digit 4’s Comp

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Scaling Complement Numbers by Powers of the Base Roughly, multiplying by b corresponds to moving radix point one place right or shifting number one place left Dividing by b roughly corresponds to a right shift of the number or a radix point move to the left one place There are 2 new issues for complement numbers 1) What is new left digit on right shift? 2) When does a left shift overflow?

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Complement sayılarının tabanın kuvveti ile genişletilmesi(scaling) B ile çarpmak, radix point(kesir noktası) i bir konum sağa hareketi veya sayının bir konum sola ötelenmesi demektir B ile bölmek, radix point i bir konum sola harekeri veya sayının bir konum sağa ötelenmesidir Burada complement sayıları ile ilgili 2 yeni konu oluşur 1) What is new left digit on right shift? 2) When does a left shift overflow?

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Right Shifting a Complement Number to Divide by b For positive x m-1 x m-2...x 1 x 0, dividing by b corresponds to right shift with zero fill 0x m-1 x m-2...x 1 For negative x m-1 x m-2...x 1 x 0, dividing by b corresponds to right shift with b-1 fill (b-1)x m-1 x m-2...x 1 This holds for both b’s and b-1’s comp. systems

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Right Shifting a Complement Number to Divide by b Pozitif için x m-1 x m-2...x 1 x 0, b ile bölme, 0 ile doldurarak sağa ötelemedir 0x m-1 x m-2...x 1 Negetif için x m-1 x m-2...x 1 x 0, b ile bölme b-1 ile doldurarak sağa ötelemedir (b-1)x m-1 x m-2...x 1 Bu b’s ve b-1’s complement sistemlerindedir

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Complement Number Overflow on Left Shift to Multiply by b For positive numbers, overflow occurs if any digit other than 0 shifts off left end Positive numbers also overflow if the digit shifted into left position makes number look negative, i.e. digit ≥ b/2 for even b For negative numbers, overflow occurs if any digit other than b-1 shifts off left end Negative numbers also overflow if new left digit makes number look positive, i.e. digit<b/2 for even b

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Complement Number Overflow on Left Shift to Multiply by b Pozitif sayılar için, Eğer 0 dan farklı herhangi bir basamak en sola ötelenirse overflow olur Eğer sola ötelenen rakam sayıyı negeatif görünüme geçirise, Positive sayılar overflow olur., i.e. digit ≥ b/2 for even b Negative sayılar için, Eğer b-1 den farklı bir basamak en sola ötelenirse overflow oluşur Eğer yeni basamak sayıyı pozitif görünümlü yaparsa overflow olur, i.e. digit<b/2 for even b

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Left Shift Examples With Radix Complement Numbers Non-overflow cases: Left shift of = 620 8, becomes Left shift of = 310 8, becomes Overflow cases: Left shift of = shifts 2  0 off left Left shift of = changes from + to - Left shift of = changes from - to + Left shift of = shifts 6  7 off left

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fixed Point Addition and Subtraction If the radix point is in the same position in both operands, addition or subtraction act as if the numbers were integers Addition of signed numbers in radix complement system needs only an unsigned adder So we only need to concentrate on the structure of an m digit, base b unsigned adder

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fixed Point Addition and Subtraction Eğer radix point, toplama ve çıkarma işlemleri için aynı pozisyondaysa toplama ve çıkarma gerçekleşir radix complement sisteminde signed number ların toplanması bir unsigned toplayıcı ya ihtiyaç duyar Böylece biz sadece m basamak yapısına, base b unsigned adder a dikkat etmeliyiz

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 6.1 An m-digit base B unsigned adder Typical cell produces s j = (x j + y j + c j ) mod b and c j+1 =  (x j + y j + c j )/b  Since x j, y j ≤ b-1, c j ≤ 1 implies c j+1 ≤ 1, and since c 0 ≤ 1, all carries are ≤1, regardless of b

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Unsigned Addition Examples If result can only have a fixed number of bits, overflow occurs on carry from leftmost digit A table of sum and carry for each of the b 2 digit pairs, and one for carry in = = A2C = BE2 16 Overflow Carry for 16 bit Sum = E 16 word Base

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Unsigned Addition Examples Eğer sonuç sadece sabit sayıda bit e sahipse, en sol basamakdan carry (elde)’de overflow olur Her b 2 basamak ikilieri için toplam ve carry(elde) tablosu, and one for carry in = = A2C = BE2 16 Overflow Carry for 16 bit Sum = E 16 word Base

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Implementation Alternatives for Unsigned Adders If b = 2 k, then each base b digit is equivalent to k bits A base b digit adder can be viewed as a logic circuit with 2k+1 inputs and k+1 outputs This combinational logic circuit can be designed with as few as 2 levels of logic PLA, ROM, and multi-level logic are also alternatives s xy c0c0 c1c1 Fig 6.1a

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Implementation Alternatives for Unsigned Adders If b = 2 k ise,her taban b basamağı k bit e eşittir Bir base b adder sk+1 inputlu ve k+1 outputlu bir logic devre ile gösterilir. This combinational logic circuit can be designed with as few as 2 levels of logic PLA, ROM, and multi-level logic are also alternatives s xy c0c0 c1c1 Fig 6.1a

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 6.2 base b Complement Subtracter To do subtraction in the radix complement system, it is only necessary to negate (radix complement) the 2nd operand It is easy to take the diminished radix complement, and the adder has a carry in for the +1

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 6.2 base b Complement Subtracter Radix complement de Çıkarma yapmak için, sadece ikinci operand ı negate etmemiz yeterldir. diminished radix complement in alınması kolaydır ve adder +1 için bir carry e sahiptir.

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig ’s Complement Adder/Subtracter

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Speeding Up Addition With Carry Lookahead Speed of digital addition depends on carries A base b = 2 k divides length of carry chain by k Two level logic for base b digit becomes complex quickly as k increases If we could compute the carries quickly, the full adders compute result with 2 more gate delays Carry lookahead computes carries quickly It is based on two ideas: - a digit position generates a carry - a position propagates a carry in to the carry out

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Speeding Up Addition With Carry Lookahead Toplama işleminin hızı carry lere bağlıdır A base b = 2 k divides length of carry chain by k Base b basamak için two level logic kompleks olur, k nın hızlı artması durumunda Eğer carry leri hızlı hesaplarsak, the full adders compute result with 2 more gate delays Carry lookahead carry leri hızlıca hesaplar Bu iki fikre bağlıdır: - a digit position generates a carry - a position propagates a carry in to the carry out

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 6.4 Carry Lookahead Adder for Group Size k = 2

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 6.5 Digital Multiplication Schema p: product pp: partial product

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 6.6 Parallel Array Multiplier for Unsigned Base b Numbers

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig ’s Complement Signed Multiplier Hardware

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Branching on Arithmetic Conditions An ALU with two m bit operands produces more than just an m bit result The carry from the left bit and the true/false value of 2’s complement overflow are useful There are 3 common ways of using outcome of compare (subtract) for a branch condition 1) Do the compare in the branch instruction 2) Set special condition code bits and test them in the branch 3) Set a general register to a comparison outcome and branch on this logical value

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Branching on Arithmetic Conditions 2 m bit operand lı ALU m bit den daha büyük bir sonuç üretir Sol bitden gelen carry ve 2’s complement overflow unun true/flase değeri kullanılır There are 3 common ways of using outcome of compare (subtract) for a branch condition 1) karşılaştırmayı, dallanma komutunda yapın 2) özel durum kodu bitleri set edin ve bunları her dallanma da test edin 3) sonucu ve dallanma daki logic değeri karşılaştırmak için genel bir register set edin

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Drawbacks of Condition Codes Condition codes are extra processor state set, and overwritten, by many instructions Setting and use of CCs also introduces hazards in a pipelined design CCs are a scarce resource they must be used before being set again CCs are processor state that must be saved and restored during exception handling

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Durum Kodlarının Dezavantajı Condition code lar extra işlemci durumudur set, and overwritten, by many instructions CC lerin kullanılması ve set edilmesi, pipeline dizayn da hazard lara sebep olabilir CC ler sınırlı bulunan kaynaklardır they must be used before being set again CC ler, saklanması gereken ve istisna yakalama da restore edilmesi gerken işlemci durumlarıdır.

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Drawbacks of Comparison in Branch and Set General Register Branch instruction length: it must specify 2 operands to be compared, branch target, and branch condition (possibly place for link) Amount of work before branch decision: it must use the ALU and test its output—this means more branch delay slots in pipeline Setting a general register to a particular outcome of a compare, say ≤ unsigned, uses a register of 32 or more bits for a true/false value

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Drawbacks of Comparison in Branch and Set General Register Dallanma komut uzunluğu: 2 operand ın karşılaştırılması gerekir, dallanma hedefi ve dallanma durumu(muhtemelen link için yer) Dallanma kararı öncesi iş yükü: ALU kullanılmalı ve output lar test edilmeli- pipeline da daha fazla dallanma gecikmesi demek Bir genel register ın, bir karşılaştırma sonucuna set edilmesi, ≤ unsigned true/false değeri için 32 veya daha fazla bitlik register kullanır

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall ALU Logical, Shift and Rotate Instructions Shifts are often combined with logic to extract bit fields from, or insert them into, full words A MC68000 example extracts bits of a 32 bit word (exponent of a floating point #) MOVE.L D0, D1 ;Get # into D1 ROL.L #9, D1 ;exponent to bits 7..0 ANDI.L #FFH, D1 ;clear bits 31..8

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall ALU Logical, Shift and Rotate Instructions Shift ler çoğu kez bit alanlarının aktarılması veya full word lere eklenmesi için logic ile birleştirilir A MC68000 example extracts bits of a 32 bit word (exponent of a floating point #) MOVE.L D0, D1 ;Get # into D1 ROL.L #9, D1 ;exponent to bits 7..0 ANDI.L #FFH, D1 ;clear bits 31..8

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Types and Speed of Shift Instructions Rotate right is equivalent to rotate left with a different shift count Rotates can include the carry or not Two right shifts, one with sign extend, are needed to scale unsigned and signed numbers Only a zero fill left shift is needed for scaling Shifts whose execution time depends on the shift count use a single bit ALU shift repeatedly Fast shifts, important for pipelined designs, can be done with a barrel shifter

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Types and Speed of Shift Instructions Rotate right, farklı shift sayısında ki rotate lieft ile eşittir Rotates can include the carry or not Two right shifts, birisi sign extend ile, bunlar unsigned veya signed number ların ayarlanmasına ihtiyaç duyar Sadece bir zero fill left shift scale(ayarlanma-ölçeklendirme) için gereklidir Bütün işlemin shift edilme zamanı, shift sayısına bağlıdır. Hızlı shift ler, pipeline dizayn için önemlidir, barrel shifter ile yapılabilir.

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 6.11 A 6 Bit Crossbar Barrel Rotator for Fast Shifting

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Elements of a Complete ALU In addition to the arithmetic hardware, there must be a controller for multi-step operations, such as series parallel multiply The shifter is usually a separate unit, and may have lots of gates if it is to be fast Logic operations are usually simple The arithmetic unit may need to produce condition codes as well as a result number Multiplexers select the result and condition codes from the correct sub-unit

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Elements of a Complete ALU Aritmetic donanıma ek olarak, multi-step operation lar için bir controller olmak zorundadır, örneğin paralel çarpma serileri Shifter ayrık bir birimdir, ve hızlı olması için pek çok kapıları vardır Logic operations genelde basittir. arithmetic unit durum kodları üretmeye ihtiyaç duyabilir as well as a result number Multiplexers sonucu ve durum kodlarını seçer doğru alt birimden

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 6.13 Complete Arithmetic Logic Unit Block Diagram

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Floating Point Preliminaries: Scaled Arithmetic Software can use arithmetic with a fixed binary point position, say left end, and keep a separate scale factor e for a number f  2 e Add or subtract on numbers with same scale is simple, since f  2 e + g  2 e = (f+g)  2 e Even with same scale for operands, scale of result is different for multiply and divide (f  2 e )  (g  2 e ) = (f  g)  2 2e ; (f  2 e )  (g  2 e ) = f  g Since scale factors change, general expressions lead to a different scale factor for each number—floating point representation

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Floating Point Preliminaries: Scaled Arithmetic Yazılım fixed binary point position ile aritmetik kullanabilir ve f  2 e sayısı için ayrık ölçekleme faktörü e yi saklar. Aynı ölçekteki sayılar için toplama ve çıkarma basittir, since f  2 e + g  2 e = (f+g)  2 e Aynı ölçekte ki operand lar için, sonuç skalası çarpma ve bölme için farklıdır (f  2 e )  (g  2 e ) = (f  g)  2 2e ; (f  2 e )  (g  2 e ) = f  g Skala faktörü değiştiğinden, genel ifadeler, her sayı için farklı skala faktörlerini kullanır-floating point representation

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 6.14 Floating Point Numbers Include Scale & Number in One Word All floating-point formats follow a scheme similar to the one above s is sign, e is exponent, and f is significand

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Signs in Floating Point Numbers Both significand and exponent have signs A complement representation could be used for f but sign-magnitude is most common now The sign is placed at the left instead of with f so test for negative always looks at left bit The exponent could be 2’s complement but it is better to use a biased exponent

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Signs in Floating Point Numbers Both significand and exponent have signs F için kullanılan bir complement ifadesi Fakat burada sign-magnitude çok geneldir İşaret solda bulunur Böylece negatif için test her zaman bir sol bit e bakar exponent 2’s complement olmalıdır Fakat, biased exponent kullanmak daha iyidir

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Exponent Base and Floating Point Number Range In a floating point format using 24 out of 32 bits for significand, 7 would be left for exponent A number x would have a magnitude ≤x≤2 63, or about ≤x≤10 19 For more exponent range, bits of significand would have to be given up with loss of accuracy An alternative is an exponent base >2

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Exponent Base and Floating Point Number Range Bir floating point formatı 32 bit den 24 biti significant olarak kullanır, 7 tanesi solda exponent içindir Bir x sayısı ≤x≤2 63 magnitude u vardır Veya ≤x≤10 19 Daha fazla exponent alanı için, significant bitler doğruluk kaybı ile verilir Exponent base in 2 den büyük olması bir alternatifdir

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Normalized Floating Point Numbers There are multiple representations for a FP # Scientific notation example:.819  10 3 =.0819  10 4 A normalized floating point number has a leftmost digit non- zero (exponent small as possible) Zero cannot fit this rule; usually written as all 0s

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Normalized Floating Point Numbers Bir FP # için birden fazla ifade şekli vardır Bilimsel gösterim örneği:.819  10 3 =.0819  10 4 normalized floating point number, sıfır olmayan leftmost rakama sahiptir Sıfır bu kurala uymaz

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Comparison of Normalized Floating Point Numbers If normalized numbers are viewed as integers, a biased exponent field to the left means an exponent unit is more than a significand unit The largest magnitude number with a given exponent is followed by the smallest one with the next higher exponent Normalized FP numbers can be compared for,≥,=,  as if they were integers This is the reason for the s, e, f ordering of the fields and the use of a biased exponent

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Comparison of Normalized Floating Point Numbers Eğer normalized number lar integer gibi görüntülenirse, a biased exponent field to the left means an exponent unit is more than a significand unit Verilen exponent için en büyük magnitude sayısı, bir sonraki en büyük exponent ile sonrasında gelen en küçük değerdir Normalized FP numbers can be compared for,≥,=,  as if they were integers This is the reason for the s, e, f ordering of the fields and the use of a biased exponent

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 6.15 IEEE Single-Precision Floating Point Format Exponent bias is 127 for normalized #s e e Value Type 255 none none Infinity or NaN (-1) s  (1.f 1 f 2...)  Normalized (-1) s  (1.f 1 f 2...)  Normalized (-1) s  (1.f 1 f 2...)  Normalized (-1) s  (0.f 1 f 2...)  Denormalized ^

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Special Numbers in IEEE Floating Point An all zero number is a normalized 0 Other numbers with biased exponent e = 0 are called denormalized Denorm numbers have a hidden bit of 0 and an exponent of -126; they may have leading 0s Numbers with biased exponent of 255 are used for ±  and other special values, called NaN (not a number)

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Special Numbers in IEEE Floating Point all zero number, 0 olarak normalize edilir E=0 biased exponent li diğer sayılara dernormalized denir. Denorm numbers bir tane 0 gizli bit e ve -126 exponent e sahiptir, they may have leading 0s 255 exponent ile biased edilen sayılar ±  için kullanılır, ve NaN olarak bilinir (not a number)

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 6.16 IEEE Standard Double Precision Floating Point Exponent bias for normalized #s is 1023 The denorm biased exponent of 0 corresponds to an unbiased exponent of Infinity and NaNs have a biased exponent of 2047 Range increases from about ≤|x|≤10 38 to about ≤|x|≤10 308

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 6.16 IEEE Standard Double Precision Floating Point Normalized number lar için exponenet bias 1023 dür The denorm biased exponent of 0 corresponds to an unbiased exponent of sonsuz ve NaNs sayılar 2047 biased exponent e sahiptirler. Range increases from about ≤|x|≤10 38 to about ≤|x|≤10 308

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Decimal Floating Point Add and Subtract Examples Operands AlignmentNormalize & round         10 5 Operands AlignmentNormalize & round         10 -9

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig 6.17 Floating Point Add & Subtract Hardware Adders for exponents and significands Shifters for alignment and normalize Multiplexers for exponent and swap of significands Lead zeros counter

S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Decimal Floating Point Examples for Multiply & Divide Multiply fractions and add exponents These examples assume normalized result is 0.xxx Sign, fraction & exponentNormalize & round (  )  10 2  (  10 6 )    10 2 Sign, fraction & exponentNormalize & round (  10 2 )  10 9  (  )   10 2-(-6)  10 9 Divide fractions and subtract exponents