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S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Chapter 3 Topics 3.1 Machine characteristics and performance 3.2.

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1 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Chapter 3 Topics 3.1 Machine characteristics and performance 3.2 RISC vs. CISC 3.3 A CISC example: The Motorola MC A RISC example: The SPARC

2 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Bölüm 3 Konuları 3.1 Makine özellikleri ve performansı 3.2 RSC vs. CISC 3.3 Bir CISC örneği: Motorola MC RISC örneği: SPARC

3 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Practical Aspects of Machine Cost- Effectiveness Cost for useful work is fundamental issue Mounting, case, keyboard, etc. are dominating the cost of integrated circuits Upward compatibility preserves software investment Binary compatibility Source compatibility Emulation compatibility Performance: strong function of application

4 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Makinenin Maliyet Uygunluğu Yönü Faydalı işler için maliyet temel meseldir. Mounting, case, keyboard, vs. entegre devre maliyetlerinin çoğunluğunu sağlar. Upward uyumluluk, yazılım yatırımlarının muhafaza eder İkili uyumluluk Kaynak uyumluluğu Emülasyon uyumluluğu Performans: uygulamaların güçlü fonksiyonları

5 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Performance Measures MIPS: Millions of Instructions Per Second Same job may take more instructions on one machine than on another MFLOPS: Million Floating Point OPs Per Second Other instructions counted as overhead for the floating point Whetstones: Synthetic benchmark A program made-up to test specific performance features Dhrystones: Synthetic competitor for Whetstone Made up to “correct” Whetstone’s emphasis on floating point SPEC: Selection of “real” programs Taken from the C/Unix world

6 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Performans Ölçüleri MIPS: Saniyede ki Milyon Komut Sayısı Aynı işler, farklı makinelerde çalışırken farklı sayıda komut içerebilirler. MFLOPS: Saniyede ki Milyon Küsuratlı Sayı İşlemi Other instructions counted as overhead for the floating point Whetstones: Yapay (kalite testi)benchmark Bir program özel performans niteliklerini test edebilir. Dhrystones: Whetstone için yapay rakip Made up to “correct” Whetstone’s emphasis on floating point SPEC: Gerçek programların seçimi C/Unix dünyasından alınan

7 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Quantitative Performance Measurement Consider two auto routes, the old one, which allowed an average speed of 34 mph, and the new one, which permitted 46 mph. What is the speedup of the new one over the old one? Conventionally the speedup is calculated as follows: For a speedup of 0.35, or 35%. Alternately, the % speedup can be calculated directly:

8 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Nicel Performans Ölçümü İki otomobil rotasını düşünün,eski olan 34 mph ortalama hıza, yeni olan ise ortalama 46 mph hıza kadar çıkabiliyor. Yeni arabanın, eskiye göre hızlanması nedir? Konvansiyonel hızlanma şu şekilde hesaplanır : Hızlanma 0.35 veya 35%. Alternatif olarak % şeklinde hesaplanması şu şekilde olur:

9 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Quantitative Performance Measurement Many measurements are in terms of the time, T, it takes to accomplish some task. Recall that Time, T, is the reciprocal of Speed, S= 1/T. If the improvement is measured by recording travel time rather than travel speed the equation changes as follows: Once again, the % speedup can be calculated directly:

10 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Nicel Performans Ölçümü Bazı ölçümler zaman bazında hesaplanır. T(Time), bir görevin tamamlanma süresidir. Zaman, T, hızla karşılıklıdır, S= 1/T. Eğer gelişme seyahat edilen hız yerine, zamana dayalı ölçüldüyse; denklem şu şekilde değişir: % olarak şu şeklide hesaplanır:

11 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall A Classic Example

12 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Getting Finer-Grained The execution time can be calculated from the count of how many instructions have executed, IC, the average number of clock cycles per instruction, CPI, and the clock period,  This is an important equation that will be used throughout the text.

13 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Getting Finer-Grained Uygulama zamanı ne kadar komutun çalıştırıldığı sayısına göre hesaplanır,IC, komut başına düşen ortalama clock cycle, CPI, ve period,  Bu önemli bir denklem olup, ileriki konularda kullanılacaktır.

14 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall CISC Versus RISC Designs CISC: Complex Instruction Set Computer Many complex instructions and addressing modes Some instructions take many steps to execute Not always easy to find best instruction for a task RISC: Reduced Instruction Set Computer few, simple instructions, addressing modes usually one word per instruction may take several instructions to accomplish what CISC can do in one complex address calculations may take several instructions usually has load-store, general register ISA

15 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall CISC Versus RISC Designs CISC: Kompleks komut kümeli bilgisayarlar Çok fazla kompleks komut ve adresleme şekli Bazı komutların çalışması pek çok aşamada gerçekleşir Her zaman, bir görev için en iyi komutu bulmak kolay değildir. RISC: İndirgenmiş komut kümeli bilgisayarlar Az, basit komutlar ve adresleme şekilleri Genelde her komut için bir word CISC de yapılan bir işlemi yapmak için pek çok komut kullanılır Kompleks adres hesaplamaları, pek çok komutla gerçekleştirilir Genelde load-store genel register ISA(Komut kümesi mimarisi) sine sahiptir.

16 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Design Characteristics of RISCs One instruction per cycle Fixed instruction length Fixed length instructions simplify fetch & decode Only load and store instructions access memory Simplified addressing modes Fewer, simpler operations Delayed loads, stores and branches Pre-fetch and speculative execution Compilers for RISCs have been developed with special care and attention to optimization for special RISC characteristics

17 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Design Characteristics of RISCs Cycle(devir) da bir komut Değişmez komut uzunluğu Fixed length instructions simplify fetch & decode Sadece load ve store komutları belleğe ulaşır Basitleştirilmiş adresleme şekilleri Az ve basit işlemler Geciken load, store ve dallanma Pre-fetch and speculative execution RISC derleyicileri özel itina ve dikkat ile geliştirilirler.

18 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Other RISC Characteristics Prefetching of instructions (Similar to I8086) Fetching the next instruction(s) into an instruction queue before the current instruction is complete Pipelining Beginning execution of an instruction before the previous instruction(s) have completed. (Will cover in Chapter 5.) Superscalar operation Issuing more than one instruction simultaneously (Instruction-level parallelism. Also covered in Chapter 5.) Register Windows Ability to switch to a different set of CPU registers with a single command. Alleviates procedure call/return overhead.

19 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Diğer RISC Özellikleri Prefetching of instructions (Similar to I8086) Fetch edilecek sonraki komutlar, mevcut komut işlenen kadar, bir komut kuyruğunda tutulur. Pipelining Bir önceki komutlar bitirilmeden, sonraki komutların işlenmesine başlanır. (Will cover in Chapter 5.) Superscalar işlemi Eş zamanlı olarak, birden fazla komutun işlenmesidir. (Instruction-level parallelism. Also covered in Chapter 5.) Register Windows Tek komutla farklı CPU register kümeleri arasında geçiş yapma yeteneği. Alleviates procedure call/return overhead.

20 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Table 3.1 Developing an Instruction Set Architecture Memories: structure of data storage in the computer Processor state registers Main memory organization Formats and their interpretation: meanings of register fields Data types Instruction format Instruction address interpretation Instruction interpretation: things done for all instructions The fetch-execute cycle Exception handling (sometimes deferred) Instruction execution: behavior of individual instructions Grouping of instructions into classes Actions performed by individual instructions

21 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tablo 3.1 Komut Kümesi Mimarisi Geliştirlmesi Bellekler: bilgisayar da ki veri depolama yapılarıdır İşlemci durum regsiter ları Ana Bellek organizasyonu Formatları ve Yorumlanması: register alanlarının anlamları Veri yapıları Komut format Komut adres yorumlanması Komut Yorumlanması: Bütün komutlar için yapılanlar fetch-execute döngüsü Exception yakalam (sometimes deferred) Komut işlenmesi: bireysel komutların davranışları Komutların gruplanması Bireysel komutlar tarafından gerçekleştirilen işlemler

22 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall CISC: The Motorola MC68000 Introduced in 1979 One of first 32 bit microprocessors Means that most operations are on 32 bit internal data Some operations may use different number of bits External data paths may not all be 32 bits wide MC68000 had a 24 bit address bus Complex Instruction Set Computer - CISC Large instruction set 14 addressing modes

23 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall CISC: The Motorola MC68000 Introduced in bitlik mikroişlemcilerdendir Pek çok işlemler 32 bitlik dahili veridedir Bazı işlemler farklı sayıda bit kullanabilirler Harici veri yolları 32 bit genişliğinde olmayabilir MC bit adres yolu vardır Kompleks Komut Kümeli bilgisayar - CISC Geniş Komut Kümesi 14 adresleme şekli

24 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 3.1 MC68000 Programmer’s Model

25 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Features of the Processor State Distinction between 32 bit data registers and 32 bit address registers 16 bit instruction register Variable length instructions handled 16 bits at a time Stack pointer registers User stack pointer is one of the address registers System stack pointer is a separate single register Discuss: Why a separate system stack. Condition code register: System & User bytes Arithmetic status (N, Z, V, C, X) is in user status byte System status has Supervisor & Trace mode flags, as well as the Interrupt Mask

26 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall İşlemci durumunun özellikleri 32 bitlik veri regsiter ları ile 32 bitlik adres register larının farkı 16 bit komut register Değişken uzunluktaki komutları 16 bit da tutulur Stack pointer registers Kullanıcı stack pointer bir adres register idir. Sistem stack pointer ayrı tekil register dır. tartışma: neden ayrık system stack. Durum Kodu Register: System & User bytes Aritmetik durumlar (N, Z, V, C, X) System status has Supervisor & Trace mode flags, as well as the Interrupt Mask

27 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Supports Several Operand Types Like many CISC machines, the allows one instruction to operate on several types MOVE.B for bytes, MOVE.W for words, and MOVE.L for longwords; also ADD.B, ADD.W, ADD.L, etc. Bits coding operand type vary with instruction

28 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Pek Çok Operand Tipini Destekler Pek çok CISC makinesinde olduğu gibi, bir komutu pek çok tipte işlemeye izin verir MOVE.B byte için, MOVE.W word için, ve MOVE.L longwords için; also ADD.B, ADD.W, ADD.L, etc. Bit kodlama operand tipi, komutlar arasında değişiklik arz eder

29 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 3.2 Some MC68000 Instruction Formats

30 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall General Form of Addressing Modes in the MC68000 A general address of an operand or result is specified by a 6-bit field with mode and register numbers Not all operands and results can be specified by a general address: some must be in registers modereg Provides access paths to operands

31 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000’da Adresleme Şekillerinin Genel Formları Bir operand veya sonucun genel adresi, mode ve register numarası olmak üzere 6 bitle gösterilir. Bütün opeand lar ve sonuçlar genel adresleme ile gösterilmeyebilir: bazıları register da olmak zorundadır modereg Operand a ulaşım yolu sağlar

32 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Adresleme şekilleri modereg

33 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tbl. 3.3 MC68000’da Veri Aktarım Komutları The op code location and size depends on the instruction Op Code’ un yeri ve boyutu komuta bağlıdır.

34 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Integer Arithmetic and Logic Instructions Op.Operands Inst. wordX N Z V C OperationSizes ADDEA,Dn1101rrrmmmaaaaaax x x x x dst  dst+srcb, w, l SUBEA,Dn1001rrrmmmaaaaaax x x x x dst  dst-srcb, w, l CMPEA,Dn1011rrrxxxaaaaaa - x x x x dst-srcb, w,l CMPI#dat,EA wwaaaaaa- x x x x dst-imm.datab, w, l MULSEA, Dn1100rrr111aaaaaa - x x 0 0 Dn  Dn*srcl  w*w MULUEA,Dn1100rrr011aaaaaa- x x 0 0 Dn  Dn*srcl  w*w DIVS EA,Dn1000rrr111aaaaaa- x x x 0 Dn  Dn/srcl  l/w DIVUEA,Dn1000rrr011aaaaaa- x x x 0 Dn  Dn/srcl  l/w ANDEA,Dn1100rrrmmmaaaaaa- x x 0 0 dst  dst  srcb, w, l OR EA,Dn1000rrrmmmaaaaaa- x x 0 0 dst  dst  srcb, w, l EOR EA,Dn1011rrrwwwaaaaaa- x x 0 0 dst  dst  srcb, w, l CLR EAs wwaaaaaa dst  0 b, w, l NEGEAs wwaaaaaa- x x x x dst  0-dstb, w, l TST EAs wwaaaaaa- x x 0 0 dst  0b, w, l NOTEAs wwaaaaaa- x x x x dst  dstb, w, l aaaaaa is the 6-bit addressing mode specifier mmmrrr www: B–100, W–101, L–110 xxx: B–000, W–001, L–010

35 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Arithmetic Shifts and Single Word Rotates d is L or R for left or right shift, respectively EA form has shift count of 1 ww is word size: 00–Byte, 01–Word, 10–Long Word Op.Operands Inst. wordXNZVC ASdEA d11aaaaaaxxxxx ASd#cnt,Dn1110cccdww000rrrxxxxx ASdDm,Dn1110RRRdww100rrrxxxxx ROdEA d11aaaaaa-xx0x ROd#cnt,Dn1110cccdww011rrr-xx0x ROdDm,Dn1110RRRdww111rrr-xx0x

36 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Aritmetik Öteleme ve Tek Word Döndürme d L veya R olabilir, sağa veya sola ötelemeye göre EA form has shift count of 1 ww word boyutudur: 00–Byte, 01–Word, 10–Long Word Op.Operands Inst. wordXNZVC ASdEA d11aaaaaaxxxxx ASd#cnt,Dn1110cccdww000rrrxxxxx ASdDm,Dn1110RRRdww100rrrxxxxx ROdEA d11aaaaaa-xx0x ROd#cnt,Dn1110cccdww011rrr-xx0x ROdDm,Dn1110RRRdww111rrr-xx0x

37 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Logical Shifts and Extended Rotates Field ww specifies byte, word, or longword N & Z set according to result, C= last bit shifted out Op.OperandsInst. wordXNZVC LSdEA d11aaaaaaxxx0x LSd#cnt,Dn1110cccdww001rrrxxx0x LSdDm,Dn1110RRRdww101rrrxxx0x ROXdEA d11aaaaaaxxx0x ROXd#cnt,Dn1110cccdww010rrrxxx0x ROXdDm,Dn1110RRRdww110rrrxxx0x

38 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Logical Öteleme ve Genişletilmiş Döndürme ww alanı byte, word, veya longword belirtir. N & Z sonuca göre ayarlanır, C= dışarı ötelenen son bit Op.OperandsInst. wordXNZVC LSdEA d11aaaaaaxxx0x LSd#cnt,Dn1110cccdww001rrrxxx0x LSdDm,Dn1110RRRdww101rrrxxx0x ROXdEA d11aaaaaaxxx0x ROXd#cnt,Dn1110cccdww010rrrxxx0x ROXdDm,Dn1110RRRdww110rrrxxx0x

39 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Conditions That Can Be Evaluated for Branch, Etc. CodeMeaningNameFlag expression 0000trueT1 0001falseF0 0100carry clearCCC 0101carry setCSC 0111equalEQZ 0110not equalNEZ 1011minusMIN 1010plusPLN 0011 † low or sameLSC+Z 1101less thanLTN·V+N·V 1100greater or equalGEN·V+N·V 1110greater thanGTN·V·Z+N·V·Z 1111less or equalLEN·V+N·V+Z 0010 † highHIC·Z 1000overflow clearVCV 1001overflow setVSV † Assumes unsigned operands

40 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Conditions That Can Be Evaluated for Branch, Etc. KodAnlamı Bayrak Açıklama 0000doğruT1 0001yanlışF0 0100artan temizCCC 0101artan var CSC 0111eşitEQZ 0110Eşit değilNEZ 1011eksiMIN 1010artıPLN 0011 † düşük veya aynıLSC+Z 1101Daha azLTN·V+N·V 1100Fazla veya eşitGEN·V+N·V 1110Daha fazlaGTN·V·Z+N·V·Z 1111Daha az veya eşitLEN·V+N·V+Z 0010 † yüksekHIC·Z 1000Taşma yokVCV 1001Taşma varVSV † işaretsiz operand ları düşünün

41 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Subroutine Return Instructions Subroutine linkage uses stack for return address LINK and UNLK allocate and de-allocate multiple word stack frames Op.OperandsInst. wordOperation RTR CC  (SP)+; PC  (SP)+ RTS PC  (SP)+ LINKAn,disp rrr-(SP)  An; An  SP; DDDDDDDDDDDDDDDDSP  SP + disp UNLKAn rrr SP  An; An  (SP)+

42 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Altprogram Return Komutları Adres döndürmesi için altprogram bağlantı yığın(stack) kullanır LINK ve UNLK allocate and de-allocate multiple word stack frames Op.OperandsInst. wordOperation RTR CC  (SP)+; PC  (SP)+ RTS PC  (SP)+ LINKAn,disp rrr-(SP)  An; An  SP; DDDDDDDDDDDDDDDDSP  SP + disp UNLKAn rrr SP  An; An  (SP)+

43 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Pseudo Operations in the MC68000 Assembler A Pseudo Operation is one that is performed by the assembler at assembly time, not by the CPU at run time. EQU defines a symbol to be equal to a constant. Substitution is made at assemble time. PiEQU3.14 DS.B (.W or.L) defines a block of storage Line DS.B 132 # symbol indicates the value of the symbol instead of a location addressed by the symbol MOVE.L #1000, D0 ;moves 1000 to D0 MOVE.L 1000, D0;moves value at addr to D0 ORG specifies a memory address as the origin where the following code will be stored StartORG$4000;next instruction/data will be loaded at ;address 4000H.

44 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Assembler da Pseudo İşlemleri Bir Pseudo Operation assebmly zamanında, assembler tarafından gerçekleştirilir, CPU tarafından run time da değil EQU bir sembolün bir sabite eşit olduğunu ifade eder. Substitution is made at assemble time. PiEQU3.14 DS.B (.W or.L) depo bloğunu ifade eder Line DS.B 132 # symbol indicates the value of the symbol instead of a location addressed by the symbol MOVE.L #1000, D0 ;1000’i D0 a taşı MOVE.L 1000, D0;1000 adresindeki değeri D0 a taşı ORG bir sonraki kodun depolandığı bellek adresini ifade eder StartORG$4000;bir sonraki komut veya veri ;4000 adresinde dir

45 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Review of Assembly, Link, Load, and Run Times At assemble time assembly language text is converted to (binary) machine language They may be generated by translating instructions, hexadecimal or decimal numbers, characters, etc. Addresses are translated by way of a symbol table Addresses are adjusted to allow for blocks of memory reserved for arrays, etc. At link time separately assembled modules are combined & absolute addresses assigned At load time the binary words are loaded into memory At run time the PC is set to the starting address of the loaded module. (Usually the O.S. makes a jump or procedure call to that address.)

46 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Review of Assembly, Link, Load, and Run Times assemble zamanında Assembly dili makine diline çevrilir Komutların, onaltılık ve ondalık sayıların, karakterlerin, vs.. çevirilmesiyle oluşturulur. Adresler, sembol tablosu tarafından çevrililikler. Adresler, diziler..vs gibi veri yapıları için bellek blokları rezerve edilmesine izin verecek şekilde uyarlanır. link zamanında Ayrışık şekilde assemble edilmiş modüller birleştirilir ve mutlak adresler atanır load zamanında İkilik word ler belleğe yüklenir run zamanında PC’ye yüklenen modülün başlangıç adresi atanır. (Usually the O.S. makes a jump or procedure call to that address.)

47 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Exceptions: Changes to Sequential Instruction Execution Exceptions, also called interrupts, cause next instruction fetch from other than PC location Address supplying next instruction called exception vector Exceptions can arise from instruction execution, hardware faults, and external conditions Externally generated exceptions usually called interrupts Arithmetic overflow, power failure, I/O operation completion, and out of range memory access are some causes A trace bit =1 causes an exception after every instruction Used for debugging purposes

48 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Exceptions: Changes to Sequential Instruction Execution Exception lar, interrupt olarak da adlandırılabilir, PC de bulunan komutun kesilip, başka bir komutun çalıştırılmasını sağlarlar Bir sonraki komutu sağlayan adres’e excepton vektör denir. Exception lar komut işlemesinden, donanım hataları ve dış etkenlerden meydana gelirler. Dışardan oluşturulan exception lara interrupt denir. Artimetik taşma, güç hatası, I/O işlemi bitmesi, ve belleğe ulaşma sorunları Bir bit,n bütün komutlarda sonra exception oluşasına sebep olailir Hata denetim işleminde kullanıldığı gibi

49 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Steps in Handling MC68000 Exceptions 1) Status change Temporary copy of status register is made Supervisor mode bit S is set, trace bit T is reset 2) Exception vector address is obtained Small address made by shifting 8 bit vector number left 2 Contents of the longword at this vector address is the address of the next instruction to be executed The exception handler or interrupt service routine starts there 3) Old PC and Status register are pushed onto supervisor stack 4) PC is loaded from exception vector address When several exceptions occur at once, which exception vector is used? Exceptions have priorities, and highest priority exception supplies the vector

50 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall MC68000 Exception larının Yakalanması 1) Durum değişikliği Geçici durum register ının kopyasının alınması Supervisor mode bit S is set, trace bit T is reset 2) Exception vector adresinin elde dilmesi Small address made by shifting 8 bit vector number left 2 Bu vektör adresinde, longword ün içeriği, bir sonra işlencek komutun adresidir exception handler veya interrupt service routine burada çalışır 3) Eski PC ve Durum Register’ı supervisor stack e eklenir. 4) PC, exception vector adresinden yüklenir. Pek çok exception aynı anda olduğu zaman, hangi exception vektörü kullanılır? Exception lar önceliğe sahiptirler, ve en yüksek öncelikli exception vektörü sağlar

51 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Memory Mapped I/O in the MC68000 Memory mapped I/O allows  processor chip to have one bus for both memory and I/O Multiple wires for both address and data I/O uses address space that could otherwise contain memory Not popular with machines having limited address bits Sizes of I/O & memory “spaces” independent Many or few I/O devices may be installed Much or little memory may be installed Spaces are separated by putting I/O at top end of the address space

52 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Memory Mapped I/O in the MC68000 Memory mapped I/O, mikroişlemci çipine hem bellek hem de I/O için tek veri yolu sağlar. Birden çok kablo hem adres hem de veri için I/O, belleği içeren adres alanı kullanır. Not popular with machines having limited address bits I/O nun boyutu & bellek “alanları” bagımsızdır Az veya çok I/O aracı yüklenebilir Az veya çok bellek yüklenebilir Spaces are separated by putting I/O at top end of the address space

53 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall The SPARC (Scalable Processor Architecture) as a RISC Microprocessor Architecture The SPARC is a general register, Load/Store architecture It has only two addressing modes. Address = (Reg+Reg), or (Reg + 31-bit constant) Instructions are all 32 bits in length SPARC has 69 basic instructions Separate floating point register set First implementation had a 4 stage pipeline Some important features not inherently RISC Register windows:separate but overlapping register sets available to calling and called routines 32 bit address, big-endian organization of memory

54 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall The SPARC (Scalable Processor Architecture) as a RISC Microprocessor Architecture SPARC genel register, Load/Store mimarisi Sadece iki adres şekli vardır. Adres= (Reg+Reg), veya (Reg + 31-bit sabit) Komutların hepsi 32 bit uzunluğundadır SPARC 69 basit komutu vardır Separate floating point register set İlk implementasyonu 4 aşama pipeline içerir Bazı önemli özellikleri RISC den gelmez Register windows: ayrıktır fakat örtüşen register kümeleri programları çağırmaya uygundur. 32 bit adresler, belleğin big-endian organizasyonu

55 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig. 3.9 The SPARC Processor State

56 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig Register Windows: An Important Concept in SPARC

57 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall SPARC Operand Addressing One mode computes address as sum of 2 registers; G0 gives zero if used The other mode adds sign extended 13 bit constant to a register These can serve several purposes Indexed: base in one reg., index in another Register indirect: G0+Gn Displacement: Gn+const, n  0 Absolute: G0+const. Absolute addressing can only reach the bottom or top 4K bytes of memory

58 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall SPARC Operand Adresleme Bir şekil adresleri 2 register ın toplamı olarak hesaplar; eğer kullanılıyorsa, G0 sıfır verir Diğer şekil işaretli genişletilmiş 13 bit sabiti, register a ekler Bunlar pek çok özellik sunarlar Indexed: base in one reg., index in another Register indirect: G0+Gn Displacement: Gn+const, n  0 Absolute: G0+const. Mutlak adresleme sadece belleğin üstteki veya alttaki 4K byte larına ulaşabilir.

59 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig SPARC Instruction Formats Three basic formats with variations

60 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tbl. 3.8 SPARC Veri Hareket Komutları Inst.Op.OPCODEMeaning ldsb Load signed byte ldsh Load signed halfword ldsw Load signed word ldub Load unsigned byte lduh Load unsigned halfword ldd Load doubleword stb Store byte sth Store halfword stw Store word std Store double word swap Swap register with memory ar Rdst  Rsrc1 OR Rsrc2 (or immediate) sethi00Op2=100High order 22 bits of Rdst  disp22

61 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Register and Immediate Moves in the SPARC OR is used with a G0 operand to do register to register moves To load a register with a 32 bit constant, a 2 instruction sequence is used SETHI #upper22, R17 OR R17, #lower10, R17 Double words are loaded into an even register and the next higher odd one Floating point instructions are not covered, but the 32 FP registers can hold single length numbers, or bit FP, or bit FP numbers

62 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Register and Immediate Moves in the SPARC OR bir G0 operandı ile, register dan register a hareket sağlamada kullanılır Bir register a bir 32-bitlik sabiti yüklemek için, 2 komut dizisi kullanılır SETHI #upper22, R17 OR R17, #lower10, R17 Double word ler bir çift register a ve sonraki en yüksek tek olana yüklenirler Floating point komutları kapsanmaz, fakat 32 FP register lar single length numaraları tutarlar, veya bit FP, veya bit FP numaraları

63 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tbl. 3.9 Typical SPARC Arithmetic Instructions All are format 3, Op=10 CCs are set if X=1 and not if X=0 Both register and immediate forms are available Multiply is done by software using MULSCC or using floating point instructions Multiply is hard to do in one clock but multiply step is not Inst.OPCODEMeaning add0X 0000Add or add and set condition codes addc0X 1000Add with carry: set CCs or not sub0X 0100Subtract: set CCs or not subc0X 1100Subtract with borrow: set CCs or not mulscc Do one step of multiply

64 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tbl. 3.9 Tipik SPARC Aritmetik Komutları Hepsi 3 formatdadır, Op=10 CCs ler set edilir, eğer X=1 ve X=0 değilse Register ve immediate formların ikisi de uygundur Çarpma MULSCC veya floating point komut kullanan yazılım tarafından olur. Çarpmanın bir clock da olması zordur, fakat aşama aşama olur. Inst.OPCODEMeaning add0X 0000Add or add and set condition codes addc0X 1000Add with carry: set CCs or not sub0X 0100Subtract: set CCs or not subc0X 1100Subtract with borrow: set CCs or not mulscc Do one step of multiply

65 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tbl SPARC Logical and Shift Instructions All instructions use format 3 with op=10 Both register and immediate forms are available Condition codes set if S=1 & undisturbed if S=0 Inst.OPCODEMeaning AND0S 0001AND, set CCs if S=1 or not if S=0 ANDN0S 0101NAND, set CCs or not OR0S 0010OR, set CCs or not ORN0S 0110NOR, set CCs or not XOR0S 0011XNOR(Equiv), set CCs or not SLL Shift left logical, count in RSRC2 or imm13 SRL Shift right logical, count in RSRC2 or imm13 SRA Shift right arithmetic, count as above

66 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tbl SPARC Logical ve Öteleme Komutları Bütün komutlar 3 format kullanır op=10 ile register and immediate formlar ikisi de uygundur Durum kodları set edilir eğer S=1 & undisturbed if S=0 Inst.OPCODEMeaning AND0S 0001AND, set CCs if S=1 or not if S=0 ANDN0S 0101NAND, set CCs or not OR0S 0010OR, set CCs or not ORN0S 0110NOR, set CCs or not XOR0S 0011XNOR(Equiv), set CCs or not SLL Shift left logical, count in RSRC2 or imm13 SRL Shift right logical, count in RSRC2 or imm13 SRA Shift right arithmetic, count as above

67 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Pipelining of the SPARC Architecture Many aspects of the SPARC design are in support of a pipelined implementation Simple addressing modes, simple instructions, delayed branches, load/store architecture Simplest form of pipelining is fetch/execute overlap fetching next inst. while executing current inst. Pipelining breaks instruction processing into steps A step of one instruction overlaps different steps for others A new instruction is started (issued) before previously issued instructions are complete

68 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall SPARC Mimarisinde Pipelining SPARC tasarımının pek çok yönü pipeline edilmiş implementasyonları destekler Basit adresleme şekilleri, basit komutlar, bekletilen dallanmalar, load/store mimarisi En basit pipeline formu fetch/execute örtüşmesidir Mevcut komutu işlerken(execute), bir sonraki komutun alıp getirilmesi(fetch) Pipeline komut işlemlerini basamaklara böler. Bir komutun bir basamağı, diğer komutların farklı basamaklarıyla paralel işlenir. Bir komutun işlemi bitmeden, yeni bir komut işleme başlatılır.

69 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig The SPARC MB86900 Pipeline 4 pipeline stages are Fetch, Decode, Execute, and Write Results are written to registers in Write stage

70 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Fig The SPARC MB86900 Pipeline 4 pipeline durumu: Fetch, Decode, Execute, ve Write Sonuçlar, Write basamağında register lara yazılır.

71 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall CISC vs. RISC: Recap CISCs supply powerful instructions tailored to commonly used operations, stack operations, subroutine linkage, etc. RISCs require more instructions to do the same job CISC instructions take varying lengths of time RISC instructions can all be executed in the same, few cycle, pipeline RISCs should be able to finish (nearly) one instruction per clock cycle

72 S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall CISC vs. RISC: Recap CISCs genel olarak kullanılan güçlü komutları destekleri stack operations, subroutine linkage, etc. RISCs aynı işlemi gerçekleştirmek için, daha fazla komuta ihtiyaç duyar CISC komutları zaman uzunlukları açısından değişiklik gösterir RISC komutlarının hepsi aynı şeklide, az cycle ile ve pipeline olarak işlenir. RISCs bir komutu bir clock döngüsünde bitirmesi gerekir.


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